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学者姓名：杨秀芝
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Abstract ：
The sample adaptive offset (SAO) filter introduced in the high efficiency video coding standard can remove the ringing artifacts caused by the loss of high-frequency information. But, it dominates the complexity of in-loop filtering. In this article, an algorithm optimization and implementation scheme with low complexity SAO is proposed. The information statistical range is optimized regionally, which avoids the complex logic control across coding tree unit boundary, and saves additional cache structure. To trade off the complexity of SAO mode decision and the accuracy of rate model in rate-distortion optimization, a three-dimensional linear rate estimation model for fast calculation of rate-distortion cost is proposed. Finally, based on the above improved algorithms, a SAO hardware filter suitable for ultra high definition (UHD) video processing is designed. The proposed architecture supports the UHD video processing up to 333 MHz with only 85. 6 k equivalent gates. Compared with the traditional scheme, the logical resource consumption can be saved up to 71. 47% . © 2023 Science Press. All rights reserved.
Keyword ：
hardware design hardware design high efficiency video coding high efficiency video coding in-loop filtering in-loop filtering rate-distortion optimization rate-distortion optimization sample adaptive offset sample adaptive offset
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| GB/T 7714 | Chen, J. , Qin, L. , Wang, W. et al. Optimized design of sample adaptive offset filter with low complexity; [低复杂度样点自适应补偿滤波器的优化设计] [J]. | Chinese Journal of Scientific Instrument , 2023 , 44 (6) : 293-302 . |
| MLA | Chen, J. et al. "Optimized design of sample adaptive offset filter with low complexity; [低复杂度样点自适应补偿滤波器的优化设计]" . | Chinese Journal of Scientific Instrument 44 . 6 (2023) : 293-302 . |
| APA | Chen, J. , Qin, L. , Wang, W. , Yang, X. , Chen, P. . Optimized design of sample adaptive offset filter with low complexity; [低复杂度样点自适应补偿滤波器的优化设计] . | Chinese Journal of Scientific Instrument , 2023 , 44 (6) , 293-302 . |
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高效视频编码标准引入了样点自适应补偿(SAO)滤波,可去除由高频信息丢失而产生的振铃效应,但是也极大增加了环路滤波的复杂度.本文提出一种低复杂度的样点自适应补偿滤波器的算法优化和实现方案.对信息统计范围进行区域优化,避免了跨编码树单元边界的复杂逻辑控制,并节省了额外缓存结构;提出一种快速计算率失真代价的三维线性码率估计模型,以此权衡率失真优化中SAO模式决策复杂度和码率模型精确度;最后,基于上述算法改进设计了适用于超高清视频处理的SAO硬件滤波器,该架构仅以 85.6 k等效门消耗,支持高达 333 MHz主频的超高清视频处理,其逻辑资源消耗相对于传统方案最高可节省 71.47%.
Keyword ：
样点自适应补偿 样点自适应补偿 率失真优化 率失真优化 环路滤波 环路滤波 硬件设计 硬件设计 高效视频编码 高效视频编码
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| GB/T 7714 | 陈建 , 覃露 , 王卫坤 et al. 低复杂度样点自适应补偿滤波器的优化设计 [J]. | 仪器仪表学报 , 2023 , 44 (6) : 293-302 . |
| MLA | 陈建 et al. "低复杂度样点自适应补偿滤波器的优化设计" . | 仪器仪表学报 44 . 6 (2023) : 293-302 . |
| APA | 陈建 , 覃露 , 王卫坤 , 杨秀芝 , 陈平平 . 低复杂度样点自适应补偿滤波器的优化设计 . | 仪器仪表学报 , 2023 , 44 (6) , 293-302 . |
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In recent years, the resolution and frame rate of video have been continuously improved to meet people’s increasing demand for video data. However, the compression encoding speed of real-time video sequence is often restricted by frame rate and resolution. The higher the frame rate and resolution are, the longer the encoding time will be. In order to achieve real-time compression encode for video sequences with higher resolution and frame rate, this paper designed a new parallel pipeline hardware architecture of intra rate-distortion optimization prediction mode, which supports intra prediction coding of up to 64×64 coding tree unit. Firstly, a parallel scheme with 9-way prediction mode was designed. Secondly, a pipeline hardware architecture was implemented based on a 4×4 block as the basic processing unit in a Z-shaped scanning order, and the prediction data of 32×32 prediction units were reused to replace the prediction data of 64×64 prediction units so as to reduce the amount of calculation. Lastly, a new Hadamard transform circuit was proposed based on this pipelined architecture for efficient pipelined processing. The experimental results show that: on the Altera Arria 10 series field programmable gate array, the 9-way mode parallel architecture only occupies 75 kb look up table and 55 kb register resources, the main frequency can reach 207 MHz, and it only takes 4 096 clocks cycles to complete a 64×64 coding tree unit prediction and can support real-time encoding of 1 080 P resolution 99 f/s full I-frame at most. Compared with the existing design scheme, the scheme designed in this paper can realize higher frame rate 1080P real time video encoding with smaller circuit area. © 2023 South China University of Technology. All rights reserved.
Keyword ：
field programmable gate array field programmable gate array high efficiency video coding high efficiency video coding intra prediction intra prediction mode in parallel mode in parallel
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| GB/T 7714 | Lin, Z. , Ding, Y. , Yang, X. et al. Parallel Pipeline Hardware Design of Intra Rate-Distortion Optimization Prediction Mode in HEVC; [HEVC 帧内率失真优化预测模式的并行流水线硬件设计] [J]. | Journal of South China University of Technology (Natural Science) , 2023 , 51 (5) : 95-103 . |
| MLA | Lin, Z. et al. "Parallel Pipeline Hardware Design of Intra Rate-Distortion Optimization Prediction Mode in HEVC; [HEVC 帧内率失真优化预测模式的并行流水线硬件设计]" . | Journal of South China University of Technology (Natural Science) 51 . 5 (2023) : 95-103 . |
| APA | Lin, Z. , Ding, Y. , Yang, X. , Wu, L. . Parallel Pipeline Hardware Design of Intra Rate-Distortion Optimization Prediction Mode in HEVC; [HEVC 帧内率失真优化预测模式的并行流水线硬件设计] . | Journal of South China University of Technology (Natural Science) , 2023 , 51 (5) , 95-103 . |
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近年来，随着人们对视频数据需求的不断增加，视频的分辨率和帧率也在不断地提高，而实时视频序列的压缩编码速度往往受到帧率和分辨率的影响，分辨率和帧率越大，编码所需要的时间越长。为了实现更高分辨率和更高帧率的视频序列实时压缩编码，文中设计了一种新的帧内率失真优化预测模式的并行流水线硬件架构，该架构支持最大64×64编码树单元的帧内预测编码。首先设计了9路预测模式并行方案；然后，按照Z型扫描顺序实现以4×4块为基本处理单元的流水线硬件架构，并复用32×32预测单元的预测数据，用以代替64×64预测单元的预测数据，减少运算量；最后，基于该流水线架构，提出了一种新的哈达玛变换电路，用以实现高效的流水线处理。实验结果表明：在Altera Arria 10系列的现场可编程门阵列上，该9路模式并行架构仅占用75 kb的查找表和55 kb的寄存器资源，主频可以达到207 MHz，完成一个64×64编码树单元的预测仅需要4 096个时钟周期，最大能够支持1 080 P分辨率99 f/s全I帧的实时编码；与已有设计方案相比，文中方案能够用更小的电路面积实现更高帧率的1 080 P实时视频编码。
Keyword ：
帧内预测 帧内预测 模式并行 模式并行 现场可编程门阵列 现场可编程门阵列 高效视频编码 高效视频编码
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| GB/T 7714 | 林志坚 , 丁永强 , 杨秀芝 et al. HEVC帧内率失真优化预测模式的并行流水线硬件设计 [J]. | 华南理工大学学报(自然科学版) , 2023 , 51 (05) : 95-103 . |
| MLA | 林志坚 et al. "HEVC帧内率失真优化预测模式的并行流水线硬件设计" . | 华南理工大学学报(自然科学版) 51 . 05 (2023) : 95-103 . |
| APA | 林志坚 , 丁永强 , 杨秀芝 , 吴林煌 . HEVC帧内率失真优化预测模式的并行流水线硬件设计 . | 华南理工大学学报(自然科学版) , 2023 , 51 (05) , 95-103 . |
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本发明涉及一种基于HEVC标准的帧内预测模式并行硬件方法。该方法通过合理分配模式并行的方案，在硬件实现的过程中可以降低硬件复杂度，节省硬件资源，在流水线设计下，在5500个时钟周期内就能完成一个CTU的帧内预测。
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| GB/T 7714 | 林志坚 , 丁永强 , 杨秀芝 et al. 一种基于HEVC标准的帧内预测模式并行硬件方法 : CN202111545047.2[P]. | 2021-12-16 00:00:00 . |
| MLA | 林志坚 et al. "一种基于HEVC标准的帧内预测模式并行硬件方法" : CN202111545047.2. | 2021-12-16 00:00:00 . |
| APA | 林志坚 , 丁永强 , 杨秀芝 , 程勇 . 一种基于HEVC标准的帧内预测模式并行硬件方法 : CN202111545047.2. | 2021-12-16 00:00:00 . |
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为了降低HEVC视频编码标准中帧内预测的复杂度，本文提出了基于深度学习的帧内块划分提前终止算法，并利用FPGA开发板进行硬件加速。提前终止算法利用深度学习中的卷积神经网络提取帧内CTU块的纹理特征，并根据提取到的纹理特征决定帧内块划分情况，进行帧内块划分的提前终止，从而减少帧内预测的复杂度；硬件加速利用Xilinx Vitis AI开发环境实现帧内卷积神经网络的FPGA硬件部署，完成硬件加速过程。测试结果表明，与HM16.5相比，本文算法在保证性能的情况下可以降低约59.253%的编码复杂度，在经过FPGA硬件加速过程后，帧内块划分预测速度最高可达到1269.27FPS。
Keyword ：
HEVC HEVC 卷积神经网络 卷积神经网络 块划分 块划分 帧内预测 帧内预测 硬件加速 硬件加速
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| GB/T 7714 | 肖帅 , 杨秀芝 . 基于深度学习的HEVC帧内预测算法研究及FPGA硬件加速 [J]. | 广播电视网络 , 2022 , 29 (03) : 107-110 . |
| MLA | 肖帅 et al. "基于深度学习的HEVC帧内预测算法研究及FPGA硬件加速" . | 广播电视网络 29 . 03 (2022) : 107-110 . |
| APA | 肖帅 , 杨秀芝 . 基于深度学习的HEVC帧内预测算法研究及FPGA硬件加速 . | 广播电视网络 , 2022 , 29 (03) , 107-110 . |
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Recently, several in-loop filtering algorithms based on convolutional neural network (CNN) have been proposed to improve the efficiency of HEVC (High Efficiency Video Coding). Conventional CNN-based filters only apply a single model to the whole image, which cannot adapt well to all local features from the image. To solve this problem, an in-loop filtering algorithm based on a dynamic convolutional capsule network (DCC-net) is proposed, which embeds localized dynamic routing and dynamic segmentation algorithms into capsule network, and integrate them into the HEVC hybrid video coding framework as a new in-loop filter. The proposed method brings average 7.9% and 5.9% BD-BR reductions under all intra (AI) and random access (RA) configurations, respectively, as well as, 0.4 dB and 0.2 dB BD-PSNR gains, respectively. In addition, the proposed algorithm has an outstanding performance in terms of time efficiency.
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| GB/T 7714 | Su, LiChao , Cao, Mengqing , Yu, Yue et al. Dynamic convolutional capsule network for In-loop filtering in HEVC video codec [J]. | IET IMAGE PROCESSING , 2022 , 17 (2) : 439-449 . |
| MLA | Su, LiChao et al. "Dynamic convolutional capsule network for In-loop filtering in HEVC video codec" . | IET IMAGE PROCESSING 17 . 2 (2022) : 439-449 . |
| APA | Su, LiChao , Cao, Mengqing , Yu, Yue , Chen, Jian , Yang, XiuZhi , Wu, Dapeng . Dynamic convolutional capsule network for In-loop filtering in HEVC video codec . | IET IMAGE PROCESSING , 2022 , 17 (2) , 439-449 . |
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Recently, several convolutional neural network (CNN)-based in-loop filtering algorithms are proposed to improve the high efficiency video coding (HEVC). However, regular CNN-based filters can only apply a single model to the whole image, but a single model usually cannot adapt well to all local features in the image. To solve this problem, we propose an inloop filtering algorithm based on convolutional capsule network (CC-net), and adapt it into the HEVC hybrid video coding framework as a new in-loop filter. This article is the first to apply capsule to the filtering work of video encoding, which is proposed to use localized dynamic routing algorithm to improve the self-adaptability of the filter to different local features in the image, and we integrate the model into HEVC encoding loop. Experimentally, our proposed method brings average 7.9%, 5.4% and 4.1% BD-BR reductions under all intra, random access and low-delay P configurations, respectively, as well as, 0.4dB, 0.2dB and 0.2dB BD-PSNR gains respectively. © 2021 IEEE.
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| GB/T 7714 | Cao, Mengqing , Yu, Yue , Chen, Jian et al. Convolutional Capsule Network Based in-Loop Filter for HEVC [C] . 2022 : 1451-1457 . |
| MLA | Cao, Mengqing et al. "Convolutional Capsule Network Based in-Loop Filter for HEVC" . (2022) : 1451-1457 . |
| APA | Cao, Mengqing , Yu, Yue , Chen, Jian , Yang, Xiuzhi , Chen, Zhifeng . Convolutional Capsule Network Based in-Loop Filter for HEVC . (2022) : 1451-1457 . |
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为实现"立德树人"的教育教学目标,守好课堂一道渠,有必要将思政元素引入《数字电路》教学中.本文首先说明课程教学内容中的思政元素;接着从以情优教、线上线下混合式教学和任务驱动法三方面阐述课程思政如何进课堂;最后探讨课程评价方式对课程思政积极的影响.实践结果表明,借有形的知识传授来照亮无形的价值引领,可以达到知识教育和思政教育的有机统一.
Keyword ：
以情优教 以情优教 数字电路 数字电路 课程思政 课程思政
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| GB/T 7714 | 许秀英 , 杨秀芝 , 陈建 . 数字电路课程思政的探索与实践 [J]. | 福建电脑 , 2022 , 38 (2) : 115-118 . |
| MLA | 许秀英 et al. "数字电路课程思政的探索与实践" . | 福建电脑 38 . 2 (2022) : 115-118 . |
| APA | 许秀英 , 杨秀芝 , 陈建 . 数字电路课程思政的探索与实践 . | 福建电脑 , 2022 , 38 (2) , 115-118 . |
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Thanks to its flexible coding structure, high-efficiency video coding (HEVC) can save more coding bit rates than the previous standard, H.264. However, it also increases the complexity of integer-pixel motion estimation (IME). To speed up the encoding process, we propose a parallel spiral search (PSS) algorithm, which features the following characteristics and advantages. First, the proposed algorithm is hardware-friendly. PSS has both a fix search order that cuts the correlation between search points and a high data reuse level that facilitates the pipeline application in hardware implementation. Second, the PSS algorithm processes all prediction units (PU) blocks in parallel, which speeds up the RD calculation. Finally, the early termination strategy is proposed to end the search for unnecessary search points and further reduce search time. Experimental results show that the proposed algorithm outperforms other popular hardware-oriented IME algorithms in terms of coding speed, with the same loss of RD performance. Compared with the default full search algorithm (FSA) in the HEVC test model HM-16.7, the proposed algorithm achieves average time saving ratio of up to 92.55%, with BD-PSNR loss of 0.056 dB and an increase by 1.38% in terms of BD-BR.
Keyword ：
Hardware-friendly motion estimation Hardware-friendly motion estimation HEVC HEVC Inter prediction Inter prediction Parallel spiral search Parallel spiral search
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| GB/T 7714 | Shi, Long-Zhao , Zhang, Zhiyong , Luo, Long et al. Parallel spiral search algorithm applied to integer motion estimation [J]. | SIGNAL PROCESSING-IMAGE COMMUNICATION , 2021 , 95 . |
| MLA | Shi, Long-Zhao et al. "Parallel spiral search algorithm applied to integer motion estimation" . | SIGNAL PROCESSING-IMAGE COMMUNICATION 95 (2021) . |
| APA | Shi, Long-Zhao , Zhang, Zhiyong , Luo, Long , Yang, Xiuzhi , Chen, Zhifeng , Yang, Xiaoling et al. Parallel spiral search algorithm applied to integer motion estimation . | SIGNAL PROCESSING-IMAGE COMMUNICATION , 2021 , 95 . |
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