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学者姓名：朱文兴
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Abstract ：
This article proposes a novel analytical steady-state thermal simulation framework considering anisotropic thermal conductivity for 3-D integrated circuits (3D-ICs) that combine an adaptive rectangular discretization algorithm with a conformal meshing strategy to achieve enhanced computational efficiency and accuracy. To address the challenges of arbitrary power density distributions in modern 3D-ICs, we develop an adaptive rectangle approximation method that dynamically adjusts rectangular partition sizes based on local gradient analysis and error-controlled discretization criteria. The derived rectangular thermal sources are subsequently processed through a conformal meshing technique that preserves geometric fidelity while minimizing mesh complexity. For analytical solution derivation, we employ the domain decomposition method effectively to divide the multilayer 3-D structure into several individual layers with customized general solutions. Interlayer thermal coupling is resolved through interfacial boundary condition enforcement. Numerical simulations demonstrate that the proposed analytical thermal method achieves significant performance improvements, exhibiting 60× acceleration over conventional finite element method (FEM) implementations while maintaining a maximum absolute error (MAX) below 0.5 K across multiple benchmark cases with 3D-ICs. © IEEE. 1993-2012 IEEE.
Keyword ：
3-D integrated circuits (3D-IC) 3-D integrated circuits (3D-IC) adaptive rectangular mesh adaptive rectangular mesh Fourier series Fourier series separation of variables (SOV) separation of variables (SOV) stepwise integration stepwise integration
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| GB/T 7714 | Zhang, P. , Jia, K. , Liu, Y. et al. An Analytical 3D-IC Thermal Simulation Framework Using Adaptive Rectangular Approximation and Conformal Mesh Method [J]. | IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2025 . |
| MLA | Zhang, P. et al. "An Analytical 3D-IC Thermal Simulation Framework Using Adaptive Rectangular Approximation and Conformal Mesh Method" . | IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2025) . |
| APA | Zhang, P. , Jia, K. , Liu, Y. , Ye, C. , Huang, J. , Zhu, W. et al. An Analytical 3D-IC Thermal Simulation Framework Using Adaptive Rectangular Approximation and Conformal Mesh Method . | IEEE Transactions on Very Large Scale Integration (VLSI) Systems , 2025 . |
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. Non-convex optimization regularized with a sparsity function has many applications in machine learning and other fields. Non-convex relaxation of the sparsity function often leads to more effective sparse optimization algorithms. In this paper, we propose a new weighted regularizer to approximate the sparsity function, and derive a weighted thresholding operator for the sparse optimization problem with the regularizer. Then, iterative weighted thresholding algorithms are designed, followed with an acceleration by using Nesterov's acceleration method and non-monotone line search. Under the Kurdyka- Lojasiewicz (KL) property, the smoothness and the appropriate convexity assumptions, we prove that the two algorithms are convergent and the convergence rates are O(1/k) and O(1/k2) respectively, where k is the iteration counter. Moreover, we develop convergent practical homotopy algorithms by invoking the two iterative weighted thresholding algorithms as subroutines respectively. A series of numerical experiments demonstrate that our algorithms are superior in both average recovery rate and average running time for the sparse recovery problem, and are competitive in solution quality and average running time for the logistic regression problem, compared to state-of-the-art algorithms.
Keyword ：
homotopy technique homotopy technique iterative weighted thresholding algorithm iterative weighted thresholding algorithm sparse solution sparse solution weighted regularizer weighted regularizer
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| GB/T 7714 | Huang, Zilin , Jiang, Lanfan , Cao, Weiwei et al. NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS [J]. | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION , 2025 , 21 (5) : 3541-3579 . |
| MLA | Huang, Zilin et al. "NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS" . | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION 21 . 5 (2025) : 3541-3579 . |
| APA | Huang, Zilin , Jiang, Lanfan , Cao, Weiwei , Zhu, Wenxing . NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS . | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION , 2025 , 21 (5) , 3541-3579 . |
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Timing-driven routing is crucial in complex circuit design. Existing shallow-light Steiner tree construction methods balance between wire length (WL) and source-sink path length (PL) but lack in delay. Conversely, previous delay-driven methods prioritize delay but result in longer WL and PL, making them suboptimal. In this article, we show that simultaneously reducing the WL and PL can effectively reduce the delay. Furthermore, we investigate how delay changes during the reduction of PL. Guided by the theoretical findings, we develop a rectilinear shallow-light Steiner tree construction algorithm designed to reduce delay meanwhile maintaining a bounded WL. Furthermore, a delay-driven edge shifting algorithm is proposed to fine tune the tree's topology, further reducing delay. We show that our proposed edge shifting algorithm can return a local Pareto optimal solution when repeatedly applied. Experimental results show that our algorithm achieves the lowest total delay compared to previous methods while maintaining competitive WL. Moreover, for nets with pins that have timing information, our algorithm can generate the most suitable Steiner Tree based on the timing information. In addition, extended experiments highlight the positive impact of constructing rectilinear Steiner trees with minimized total delay. Our codes will be available at https://github.com/Whx97/Delay-driven-Steiner-Tree.
Keyword ：
Capacitance Capacitance Delays Delays Design automation Design automation Elmore delay Elmore delay rectilinear Steiner tree rectilinear Steiner tree Resistance Resistance Routing Routing Salt Salt Steiner trees Steiner trees timing optimization timing optimization Topology Topology Very large scale integration Very large scale integration Wire Wire
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| GB/T 7714 | Wu, Hongxi , Li, Xingquan , Chen, Liang et al. Delay-Driven Rectilinear Steiner Tree Construction [J]. | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2025 , 44 (5) : 1928-1941 . |
| MLA | Wu, Hongxi et al. "Delay-Driven Rectilinear Steiner Tree Construction" . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 44 . 5 (2025) : 1928-1941 . |
| APA | Wu, Hongxi , Li, Xingquan , Chen, Liang , Yu, Bei , Zhu, Wenxing . Delay-Driven Rectilinear Steiner Tree Construction . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2025 , 44 (5) , 1928-1941 . |
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Thermal issues are becoming increasingly critical due to rising power densities in high-performance chip design. The need for fast and precise full-chip thermal analysis is evident. Although machine learning (ML)-based methods have been widely used in thermal simulation, their training time remains a challenge. In this article, we proposed a novel physics-informed separation of variables solver (PISOV) to significantly reduce training time for fast full-chip thermal analysis. Inspired by the recently proposed ThermPINN, we employ a least-square regression method to calculate the unknown coefficients of the cosine series. The proposed PISOV method combines physics-informed neural network (PINN) and separation of variables (SOVs) methods. Due to the matrix-solving method of PISOV, its speed is much faster than that of ThermPINN. On top of PISOV, we parameterize effective convection coefficients and power values for surrogate model-based uncertainty quantification (UQ) analysis by using neural networks, a task that cannot be accomplished by the SOV method. In the parameterized PISOV, we only need to calculate once to obtain all parameterized results of the hyperdimensional partial differential equations. Additionally, we study the impact of sampling methods (such as grid, uniform, Sobol, Latin hypercube sampling (LHS), Halton, and Hammersly) and hybrid sampling methods on the accuracy of PISOV and parameterized PISOV. Numerical results show that PISOV can achieve a speedup of 245x , and 10(4)x over ThermPINN, and PINN, respectively. Among different sampling methods, the Hammersley sampling method yields the best accuracy.
Keyword ：
Accuracy Accuracy Boundary conditions Boundary conditions Convection Convection Full-chip Full-chip Mathematical models Mathematical models Neural networks Neural networks parameterization technique parameterization technique physics-informed separation of variables method physics-informed separation of variables method Sampling methods Sampling methods Temperature distribution Temperature distribution thermal analysis thermal analysis Thermal analysis Thermal analysis Training Training training time training time Very large scale integration Very large scale integration
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| GB/T 7714 | Chen, Liang , Zhu, Wenxing , Tang, Min et al. PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis [J]. | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2025 , 44 (5) : 1874-1886 . |
| MLA | Chen, Liang et al. "PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis" . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 44 . 5 (2025) : 1874-1886 . |
| APA | Chen, Liang , Zhu, Wenxing , Tang, Min , Tan, Sheldon X. -D. , Mao, Jun-Fa , Zhang, Jianhua . PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2025 , 44 (5) , 1874-1886 . |
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This article proposes a novel fast analytical method for full chip thermal analysis with reduction from 3-D to 2-D using the effective thermal characteristic length, called stepwise integration separation of variables (SISOV). Unlike the traditional separation of variables (SOV) method, which relies heavily on numerical approximation integration for Fourier series coefficient calculation, the proposed SISOV employs analytical stepwise integration by leveraging the uniform power densities across each block. This analytical technique mitigates discretization errors typically encountered in numerical integration, enhancing the accuracy. To overcome the inefficiencies inherent in the plain SOV method, we propose an adaptive rectangular mesh strategy to discretize the chip. This approach markedly reduces the number of required meshed blocks compared to grid sampling points, leading to a more efficient calculation of coefficients. Finally, the fast SISOV method is applied in the thermal uncertainty quantification (UQ) analysis of the full chip. The numerical results show that the proposed SISOV outperforms the plain SOV method, providing a speedup ranging from 2 to 63 times. Moreover, its accuracy surpasses that of the SOV method, with a mean absolute error (MAE) of just 0.05 K, indicating a substantial improvement. The thermal conductivity UQ analysis reveals that the SISOV method and the plain SOV method can achieve 26 x and 9 x faster performance compared to COMSOL, respectively.
Keyword ：
Adaptive rectangular mesh Adaptive rectangular mesh Fourier series Fourier series full-chip full-chip separation of variables (SOV) separation of variables (SOV) stepwise integration stepwise integration thermal uncertainty quantification (UQ) analysis thermal uncertainty quantification (UQ) analysis
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| GB/T 7714 | Yin, Luqiao , Wang, Ao , Zhu, Wenxing et al. A Stepwise Integration Separation of Variables Solver for Full-Chip Thermal Uncertainty Analysis [J]. | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2024 , 14 (4) : 630-640 . |
| MLA | Yin, Luqiao et al. "A Stepwise Integration Separation of Variables Solver for Full-Chip Thermal Uncertainty Analysis" . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 14 . 4 (2024) : 630-640 . |
| APA | Yin, Luqiao , Wang, Ao , Zhu, Wenxing , Guo, Aiying , Liu, Jingjing , Tang, Min et al. A Stepwise Integration Separation of Variables Solver for Full-Chip Thermal Uncertainty Analysis . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2024 , 14 (4) , 630-640 . |
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In VLSI, a large number of vias may reduce manufacturability, degrade circuit performance, and increase layout area required for interconnection. In this paper, we propose a 3D global router V-GR, which considers minimizing the number of vias. V-GR uses a modified via-aware routing cost that considers the impact of wire density on the via. This cost function is more sensitive to the number of vias. Meanwhile, a novel multi-strategy rip-up & rerouting framework is developed for V-GR to solve the overflowed net, effectively optimizing wire length, overflow, and minimizing the number of vias. The proposed framework first leverages two proprietary routing techniques, namely the 3D monotonic routing and 3D 3-via-stack routing, to control the number of vias and reduce overflow. Additionally, the framework incorporates an RSMT-aware expanded source 3D maze routing algorithm to build routing paths with shorter wire length. Experimental results on the ICCAD'19 contest benchmarks show that, VGR achieves high-quality results, reducing vias by 8% and overflow by 7.5% in the global routing phase. Moreover, to achieve a fair comparison, TritonRoute is used to conduct detailed routing, and Innovus is used to evaluate the final solution. Comparison shows that V-GR achieves 4.7% reduction in vias and 8.7% reduction in DRV, while maintaining almost the same wire length.
Keyword ：
global routing global routing maze routing maze routing rip-up & rerouting rip-up & rerouting via via
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| GB/T 7714 | Zhang, Ping , Yao, Pengju , Li, Xingquan et al. V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 963-968 . |
| MLA | Zhang, Ping et al. "V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 963-968 . |
| APA | Zhang, Ping , Yao, Pengju , Li, Xingquan , Yu, Bei , Zhu, Wenxing . V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 963-968 . |
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With the advancement of semiconductor technologies, the acceleration of advanced EDA algorithms is receiving much attention. However, developing a faster mixed-size placer without hardware acceleration and loss of solution quality is of great challenge. In this article, we propose a novel definition of potential energy for each block for global placement based on an analytical solution of Poisson's equation. A fast approximate computation scheme for partial derivatives of the potential energy is given with considerably less computational loads than existing electrostatics-based placers. Moreover, we propose an effective and efficient occupy-aware macro legalization algorithm. Then, a mixed-size placer named Pplace-MS is developed. Compared to the existing leading mixed-size placer, Pplace-MS on average achieves 2.054 x speedup in single-threaded mode on the same machine and 2.3% reduction of scaled half-perimeter wirelength on the modern mixed-size placement benchmarks. The proposed approach can also be considered accelerated on GPU, as previous works.
Keyword ：
Global placement Global placement macro legalization (mLG) macro legalization (mLG) mixed-size design mixed-size design Poisson's equation Poisson's equation
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| GB/T 7714 | Peng, Keyu , Zhu, Wenxing . Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement [J]. | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2024 , 43 (2) : 613-626 . |
| MLA | Peng, Keyu et al. "Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement" . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 43 . 2 (2024) : 613-626 . |
| APA | Peng, Keyu , Zhu, Wenxing . Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2024 , 43 (2) , 613-626 . |
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To achieve a better partitioning of VLSI circuit, re-clustering and discrete optimization are applied to the k-way partitioning algorithm. Firstly, re-clustering is used to reduce the scale of hypergraph, i.e., the rating function value between two vertices is calculated according to the given partitionings, and vertices are clustered according to the magnitude of the rating function values. Secondly, the hypergraph is converted to a star graph, and the k-way partitioning problem is transformed to an unconstrained discrete optimization problem. In turn, an algorithm is designed to iteratively move the vertices with the largest gain. During the solution process, the balancing constraints are relaxed, allowing a solution to be temporarily in the infeasible region, which expands the solution space of the problem. The proposed algorithm, hMETIS-Kway and KaHyPar-K are tested on the same platform on the ISPD98 test benchmarks, and the min-cut and running time are compared. Experimental results show that, the proposed algorithm is superior to hMETIS-Kway, especially when k=2, for which the min-cut is reduced by 0.173 and the runtime is sped up by 0.706. The proposed algorithm has almost the same improvement effect over KaHyPar-K. © 2024 Institute of Computing Technology. All rights reserved.
Keyword ：
Clustering algorithms Clustering algorithms Graph theory Graph theory Iterative methods Iterative methods Optimization Optimization
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| GB/T 7714 | Pingmei, Pan , Xintian, Liu , Xingquan, Li et al. k-Way Partitioning Algorithm Based on Re-Clustering and Discrete Optimization [J]. | Journal of Computer-Aided Design and Computer Graphics , 2024 , 36 (3) : 473-484 . |
| MLA | Pingmei, Pan et al. "k-Way Partitioning Algorithm Based on Re-Clustering and Discrete Optimization" . | Journal of Computer-Aided Design and Computer Graphics 36 . 3 (2024) : 473-484 . |
| APA | Pingmei, Pan , Xintian, Liu , Xingquan, Li , Wenxing, Zhu . k-Way Partitioning Algorithm Based on Re-Clustering and Discrete Optimization . | Journal of Computer-Aided Design and Computer Graphics , 2024 , 36 (3) , 473-484 . |
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Routing is the most time-consuming phase in the physical design of modern integrated circuits. A carefully designed global routing needs to maximize the routability for the detailed routing while minimizing the wire length and the number of vias. In this paper, we propose a gradient ascent algorithm to solve the 3D global routing ILP model. This algorithm uses the Lagrangian-based cost update method that can more accurately reflect congestion for guiding the global router to generate a solution with fewer vias and congestion. In the gradient ascent rip-up and reroute stage, we use a DAG-based multi-pattern routing strategy to handle highly congested nets with constructed multiple routing patterns. Furthermore, we propose a congestion-aware dynamic net ordering algorithm to improve the congestion convergence of the rip-up and rerouting stage. Experimental results on ICCAD'19 contest benchmarks show that, on average our global router obtains high-quality results, reducing the number of vias by over 1% and 370.6% reduction in DRVs compared to CUGR 2.0, and outperforms TritonRoute-WXL's global routing in terms of runtime consumption and the number of vias.
Keyword ：
detailed-routability detailed-routability global routing global routing net ordering net ordering physical design physical design rip-up and reroute rip-up and reroute
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| GB/T 7714 | Jiang, Junkang , Yao, Pengju , Zhu, Wenxing . Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting [J]. | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 : 363-368 . |
| MLA | Jiang, Junkang et al. "Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting" . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 (2024) : 363-368 . |
| APA | Jiang, Junkang , Yao, Pengju , Zhu, Wenxing . Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 , 363-368 . |
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By leveraging the power of open-source software, the EDA tool offers a cost-effective and flexible solution for designers, researchers, and hobbyists alike. Open-source EDA promotes collaboration, innovation, and knowledge sharing within the EDA community. It emphasizes the role of the toolchain in accelerating the development of electronic systems, reducing design costs, and improving design quality. This paper presents an open-source EDA project, iEDA, aiming to build a basic infrastructure for EDA technology evolution and closing the industrial-academic gap in the EDA area. As the foundation for developing EDA tools and researching EDA algorithms and technologies, iEDA is mainly composed of file system, database, manager, operator and interface. To demonstrate the effectiveness of iEDA, we implement and tape out four chips of different scales (from 700k to 500M gates) on different process nodes (110nm and 28nm) with iEDA. iEDA is publicly available on the project home page https://github.com/OSCC-Project/iEDA.
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| GB/T 7714 | Li, Xingquan , Huang, Zengrong , Tao, Simin et al. iEDA: An Open-source infrastructure of EDA [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 77-82 . |
| MLA | Li, Xingquan et al. "iEDA: An Open-source infrastructure of EDA" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 77-82 . |
| APA | Li, Xingquan , Huang, Zengrong , Tao, Simin , Huang, Zhipeng , Zhuang, Chunan , Wang, Hao et al. iEDA: An Open-source infrastructure of EDA . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 77-82 . |
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