Query：
学者姓名：刘耿耿
Refining：
Year
Type
Indexed by
Source
Complex
Co-
Language
Clean All
Abstract ：
随着电子设计自动化技术的迅速发展,连续微流控生物芯片成为了目前最具前景的生化实验平台之一.该芯片通过采用内部的微阀门以及微通道来操纵体积仅为毫升或纳升的流体样品,从而自动执行混合和检测等基本的生化实验操作.为了实现正确的生化测定功能,部署于芯片内部的微阀门通常需要由基于多路复用器的控制逻辑进行管控,其通过控制通道获得来自核心输入的控制信号以实现精确切换.由于生化反应通常需要非常高的灵敏度,因此为了保证信号的即时传输,需要尽可能地减少连接每个阀门的控制路径长度,以降低信号传输的时延.此外,为了降低芯片的制造成本,如何有效减少控制逻辑中通道的总长度也是逻辑架构设计需要解决的关键问题之一.针对上述问题,提出了一种基于深度强化学习的控制逻辑布线算法以最小化信号传输时延以及控制通道总长度,从而自动构建高效的控制通道网络.该算法采用竞争深度Q网络架构作为深度强化学习框架的智能体,从而对信号传输时延和通道总长度进行权衡评估.此外,针对控制逻辑首次实现了对角型的通道布线,从根本上提高了阀门切换操作的效率并降低了芯片的制造成本.实验结果表明,所提出的算法能够有效构建高性能、低成本的控制逻辑架构.
Keyword ：
对角通道布线 对角通道布线 控制通道网络 控制通道网络 控制逻辑 控制逻辑 深度强化学习 深度强化学习 连续微流控生物芯片 连续微流控生物芯片
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 蔡华洋 , 黄兴 , 刘耿耿 . 基于深度强化学习的连续微流控生物芯片控制逻辑布线 [J]. | 计算机研究与发展 , 2025 , 62 (4) : 950-962 . |
| MLA | 蔡华洋 等. "基于深度强化学习的连续微流控生物芯片控制逻辑布线" . | 计算机研究与发展 62 . 4 (2025) : 950-962 . |
| APA | 蔡华洋 , 黄兴 , 刘耿耿 . 基于深度强化学习的连续微流控生物芯片控制逻辑布线 . | 计算机研究与发展 , 2025 , 62 (4) , 950-962 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
连续微流控生物芯片(continuous-flow microfluidic biochips,CFMBs)由于其能够自动高效地执行生化应用,成为近年来的研究热点.PathDriver+将实际的流体运输需求考虑进CFMBs设计流程中,并实现了实际的流体运输和去除,并为每个运输任务规划独立的流路径,而这些问题在之前的工作中被忽略了.但是,由于PathDriver+仅考虑了网格模型下总体布线的线长优化,而未考虑详细布线,没有充分利用CFMBs布线的灵活性.此外,PathDriver+仅考虑X型布线方式,而任意角度布线能够更有效地利用布线资源,从而缩短流通道长度.针对上述问题,提出了流路径驱动的任意角度布线算法,在考虑实际的流体运输需求的同时,提高布线资源的利用率,减少流通道的长度.首先基于Delaunay三角剖分构建搜索图,从而在保证布线质量的同时,提高布线解的搜索效率.然后,在构建的搜索图上,使用基于Dijkstra的流路径布线方法,以快速生成具有较短线长的布线结果.在布线过程中针对流通道复用和流通道交叉点数量优化问题,分别提出了通道复用策略和交叉优化策略,以进一步提高布线结果的质量.实验结果表明,与最新工作PathDriver+相比,所提算法在布线总线长、流层端口使用数量、通道交叉点数量方面分别降低了33.21%,11.04%,44.79%,通道复用率平均提高了 26.88个百分点,交叉点处引入阀门的总数量平均减少了42.01%,这表明所提算法的有效性和优越性.
Keyword ：
任意角度布线 任意角度布线 流路径规划 流路径规划 物理设计 物理设计 计算机辅助设计 计算机辅助设计 连续微流控生物芯片 连续微流控生物芯片
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 潘友林 , 郭帅 , 黄兴 et al. 流路径驱动的微流控生物芯片任意角度布线算法 [J]. | 计算机研究与发展 , 2025 , 62 (4) : 978-988 . |
| MLA | 潘友林 et al. "流路径驱动的微流控生物芯片任意角度布线算法" . | 计算机研究与发展 62 . 4 (2025) : 978-988 . |
| APA | 潘友林 , 郭帅 , 黄兴 , 刘耿耿 . 流路径驱动的微流控生物芯片任意角度布线算法 . | 计算机研究与发展 , 2025 , 62 (4) , 978-988 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
由于快速单通量量子(rapid single-flux-quantum,RSFQ)电路的高频特性,对电路的版图设计构成了巨大挑战.针对RSFQ电路的高频特性带来的电路时延问题,可以在布线阶段通过使用延时元件如无源传输线来解决.因为无源传输线的时延与它的长度近似成正比,且传输线的功耗不随着线长增加而增大,所以对于快速单通量量子电路而言长度匹配布线是一个非常重要的问题.为此,提出了一种高效的考虑长度匹配的RSFQ电路布线算法,包括3个关键策略:1)在生成初始路径时,提出了一种迂回布线的方法,在不改变初始布线空间的情况下,满足无源传输线的部分长度匹配;2)提出了一种基于区域感知的迭代资源插入策略,减少需要添加的额外资源区域;3)提出了一种考虑阻塞代价的长度匹配驱动布线策略,提高了对布线空间的资源利用.实验结果表明所提算法与现有的多端布线算法相比,布线所需的区域面积减少了 8％,运行时间减少了 36％,从而取得快速且高质量的布线结果.
Keyword ：
快速单通量量子电路 快速单通量量子电路 时序匹配 时序匹配 物理设计 物理设计 通道布线 通道布线 长度匹配 长度匹配
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 刘耿耿 , 余延涛 , 周茹平 et al. 考虑长度匹配的快速单通量量子电路布线算法 [J]. | 计算机研究与发展 , 2025 , 62 (5) : 1151-1163 . |
| MLA | 刘耿耿 et al. "考虑长度匹配的快速单通量量子电路布线算法" . | 计算机研究与发展 62 . 5 (2025) : 1151-1163 . |
| APA | 刘耿耿 , 余延涛 , 周茹平 , 魏榕山 , 徐宁 . 考虑长度匹配的快速单通量量子电路布线算法 . | 计算机研究与发展 , 2025 , 62 (5) , 1151-1163 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
As chip interconnect density increases, routing problems become increasingly complex. The routing scheme significantly impacts key performance indicators such as chip delay, power consumption, and area. In Very Large-Scale Integration (VLSI) routing, the rectilinear Steiner minimal tree is an excellent interconnect model for multi-pin nets. However, modern VLSI designs require multi-layer obstacle-avoiding routing, where wires must traverse multiple metal layers while avoiding obstacles to ensure connectivity and performance. This makes the Multi-Layer Obstacle-Avoiding Rectilinear Steiner Minimal Tree (ML-OARSMT) problem highly challenging in VLSI physical design. To address this issue, this paper proposes an ML-OARSMT construction algorithm based on deep reinforcement learning. First, a multi-layer obstacle-avoiding spanning graph is constructed by introducing vertex mapping, which connects different layers to handle the multi-layer obstacle-avoiding routing problem. Then, an agent is designed to learn edge selection for constructing the Multi-Layer Obstacle-Avoiding Steiner Tree (ML-OAST) using Double Deep Q-Network (DDQN). Finally, a post-processing stage is applied to further shorten the total wirelength through fast pruning and local optimization. Experimental results demonstrate that the proposed algorithm achieves better wirelength quality compared to state-of-the-art heuristic algorithms. Additionally, an ablation study confirms the effectiveness of DDQN in routing optimization.
Keyword ：
Deep reinforcement learning Deep reinforcement learning Machine learning Machine learning Physical design Physical design Routing Routing Steiner minimum tree Steiner minimum tree Very large-scale integration Very large-scale integration
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Huang, Xing , Zhu, Yuhan , Xu, Yanbo et al. Multi-layer obstacle-avoiding rectilinear steiner minimal tree algorithm based on deep reinforcement learning [J]. | JOURNAL OF KING SAUD UNIVERSITY COMPUTER AND INFORMATION SCIENCES , 2025 , 37 (7) . |
| MLA | Huang, Xing et al. "Multi-layer obstacle-avoiding rectilinear steiner minimal tree algorithm based on deep reinforcement learning" . | JOURNAL OF KING SAUD UNIVERSITY COMPUTER AND INFORMATION SCIENCES 37 . 7 (2025) . |
| APA | Huang, Xing , Zhu, Yuhan , Xu, Yanbo , Xie, Yajun , Liu, Genggeng . Multi-layer obstacle-avoiding rectilinear steiner minimal tree algorithm based on deep reinforcement learning . | JOURNAL OF KING SAUD UNIVERSITY COMPUTER AND INFORMATION SCIENCES , 2025 , 37 (7) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
As advanced technology nodes enter the nanometer era, the complexity of integrated circuit design is increasing, and the proportion of bus in the net is also increasing. The bus routing has become a key factor affecting the performance of the chip. In addition, the existing research does not distinguish between bus and non-bus in the complete global routing process, which directly leads to the expansion of bus deviation and the degradation of chip performance. In order to solve these problems, we propose a high-quality and efficient bus-aware global router, which includes the following key strategies: By introducing the routing density graph, we propose a routing model that can simultaneously consider the routability of non-bus and the deviation value of bus; A dynamic routing resource adjustment algorithm is proposed to optimize the bus deviation and wirelength simultaneously, which can effectively reduce the bus deviation; We propose a layer assignment algorithm consider deviation to significantly reduce the bus deviation of the 3D routing solution; And a depth-first search (DFS)-based algorithm is proposed to obtain multiple routing solutions, from which the routing result with the lowest deviation is selected. Experimental results show that the proposed algorithms can effectively reduce bus deviation compared with the existing algorithms, so as to obtain high-quality 2D and 3D routing solutions considering bus deviation.
Keyword ：
Bus deviation Bus deviation Bus routing Bus routing Global routing Global routing Layer assignment Layer assignment Physical design Physical design
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Liu, Genggeng , Wei, Ling , Yu, Yantao et al. A High-Quality and Efficient Bus-Aware Global Router [J]. | CHINESE JOURNAL OF ELECTRONICS , 2025 , 34 (2) : 444-456 . |
| MLA | Liu, Genggeng et al. "A High-Quality and Efficient Bus-Aware Global Router" . | CHINESE JOURNAL OF ELECTRONICS 34 . 2 (2025) : 444-456 . |
| APA | Liu, Genggeng , Wei, Ling , Yu, Yantao , Xu, Ning . A High-Quality and Efficient Bus-Aware Global Router . | CHINESE JOURNAL OF ELECTRONICS , 2025 , 34 (2) , 444-456 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Routability has always been a significant challenge in Very Large Scale Integration (VLSI) design. To overcome the potential mismatch between the global routing results and the detailed routing requirements, track assignment is introduced to achieve an efficient routability estimation. Moreover, with the increasing scale of circuits, the intricate interconnections among the components on the chip lead to increased timing delay in signal transmission, thereby significantly impacting the performance and reliability of the circuit. Thus, to further improve the routability of the circuit, it is also critical to realize an accurate estimation of the timing delay within the track assignment stage. Existing heuristic track assignment algorithms, however, are prone to local optimality, and thus fail to provide accurate routability estimations. In this article, we propose an enhanced scalable parallel track assignment algorithm called SPTA 2.0 for VLSI design, employing a two-stage partition strategy and considering timing delay. First, the proposed algorithm achieves efficient assignment of all wires by considering the routing information from both the global and local nets. Second, the overlap cost, the blockage cost, and the wirelength cost can be minimized to significantly improve the routability. Third, a critical wire controlling strategy is proposed to optimize signal timing delays inside nets. Finally, a two-stage partition strategy and a panel-subpanel-level parallelism are designed to further reduce the runtime, improving the scalability of the proposed methodology. Experimental results on multiple benchmarks demonstrate that the proposed method provides better routability estimations, and leads to superior track assignment solutions compared with existing algorithms.
Keyword ：
Integer linear programming Integer linear programming parallelism parallelism routability routability timing delay timing delay track assignment track assignment very large scale integra-tion very large scale integra-tion
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Cai, Huayang , Huang, Pengcheng , Liu, Genggeng et al. SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay [J]. | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS , 2025 , 30 (2) . |
| MLA | Cai, Huayang et al. "SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay" . | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 30 . 2 (2025) . |
| APA | Cai, Huayang , Huang, Pengcheng , Liu, Genggeng , Huang, Xing , Jing, Yidan , Liu, Wenhao et al. SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay . | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS , 2025 , 30 (2) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Continuous-flow microfluidic biochips (CFMBs) have become a hot research topic in recent years due to their ability to perform biochemical assays automatically and efficiently. For the first time, PathDriver+ takes the requirements of the actual fluid transportation into account in the design process of CFMBs and implements the actual fluid transport and removal, and plans separate flow paths for each transport task, which have been neglected in previous work. However, PathDriver+ does not take full advantage of the flexibility of CFMBs routing because it only considers the optimization of flow channel length for the global routing in the mesh model, except for the detailed routing. In addition, PathDriver+ only considers the X architecture, while the existing work shows that the any-angle routing can utilize the routing resources more efficiently and shorten the flow channel length. To address the above issues, we propose a flow path-driven arbitrary angle routing algorithm, which can improve the utilization of routing resources and reduce the flow channel length while considering the actual fluid transportation requirements. The proposed algorithm constructs a search graph based on constrained Delaunay triangulation to improve the search efficiency of routing solutions while ensuring the routing quality. Then, a Dijkstra-based flow path routing method is used on the constructed search graph to generate a routing result with a short channel length quickly. In addition, in the routing process, channel reuse strategy and intersection optimization strategy are proposed for the flow path reuse and intersection number optimization problems, respectively, to further improve the quality of routing results. The experimental results show that compared with the latest work PathDriver+, the length of channels, the number of ports used, and the number of channel intersections are significantly reduced by 33.21%, 11.04%, and 44.79%, respectively, and the channel reuse rate is improved by 26.88% on average, and the total number of valves introduced at intersections is reduced by 42.01% on average, which demonstrates the effectiveness of the algorithm in this paper. © 2025 Science Press. All rights reserved.
Keyword ：
High level synthesis High level synthesis
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Youlin, Pan , Shuai, Guo , Xing, Huang et al. Any-Angle Routing Algorithm for Microfluidic Biochips Driven by Flow Path [J]. | Computer Research and Development , 2025 , 62 (4) : 978-988 . |
| MLA | Youlin, Pan et al. "Any-Angle Routing Algorithm for Microfluidic Biochips Driven by Flow Path" . | Computer Research and Development 62 . 4 (2025) : 978-988 . |
| APA | Youlin, Pan , Shuai, Guo , Xing, Huang , Genggeng, Liu . Any-Angle Routing Algorithm for Microfluidic Biochips Driven by Flow Path . | Computer Research and Development , 2025 , 62 (4) , 978-988 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Routing and application mapping are critical stages in the design of continuous-flow microfluidic biochips (CFMBs). The routing stage determines the channel network connecting components and ports, while application mapping schedules fluid transportation and wash operations based on the designed biochip architecture. Existing methods typically handle these stages separately: routing focuses solely on physical metrics without considering subsequent scheduling requirements, while application mapping adopts one-shot scheduling strategies that can lead to suboptimal solutions. This paper proposes an integrated path-driven methodology that jointly optimizes routing and application mapping. For routing, we develop a hybrid particle swarm optimization algorithm that incorporates conflict awareness and channel utilization strategies. For application mapping, we introduce an iterative approach that leverages historical scheduling information to progressively optimize fluidic-handling and wash operations. Experimental results on both real and synthetic benchmarks demonstrate significant improvements over state-of-the-art methods, achieving reductions of 22.05% in total channel length, 21.79% in intersections, 21.97% in total delay time, and 8.30% in biochemical reaction completion time. The proposed methodology provides an effective solution for the automated design of CFMBs with enhanced physical and operational efficiency.
Keyword ：
application mapping application mapping conflict awareness conflict awareness continuous-flow microfluidic biochips continuous-flow microfluidic biochips particle swarm optimization particle swarm optimization routing routing
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Chen, Zhisheng , Liu, Bowen , Su, Hongjin et al. A Path-Driven Fluid Routing and Scheduling Method for Continuous-Flow Microfluidic Biochips with Delay Time Optimization [J]. | MICROMACHINES , 2025 , 16 (6) . |
| MLA | Chen, Zhisheng et al. "A Path-Driven Fluid Routing and Scheduling Method for Continuous-Flow Microfluidic Biochips with Delay Time Optimization" . | MICROMACHINES 16 . 6 (2025) . |
| APA | Chen, Zhisheng , Liu, Bowen , Su, Hongjin , Chen, Zhen , Liu, Genggeng , Huang, Xing . A Path-Driven Fluid Routing and Scheduling Method for Continuous-Flow Microfluidic Biochips with Delay Time Optimization . | MICROMACHINES , 2025 , 16 (6) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Continuous-flow microfluidic biochips (CFMBs) automatically execute various bioassays by precisely controlling the transport of fluid samples, which is driven by pressure delivered through fluidic ports. High-level synthesis, as an important stage in the design flow of CFMBs, generates binding and scheduling solutions whose quality directly affects the efficiency of the execution of bioassays. Existing high-level synthesis methods perform numerous transport tasks concurrently to increase efficiency. However, fluidic ports cannot be shared between concurrently executing transport tasks, resulting in a large number of fluidic ports introduced by existing methods. Increasing the number of fluidic ports undermines the integration, reduces the reliability, and increases the manufacturing cost. In this paper, we propose a port-driven high-level synthesis method based on integer linear programming (ILP) called SlimPort, integrating the optimization of fluidic port number into high-level synthesis, which has never been considered in prior work. Meanwhile, to ensure bioassay correctness, volume management between devices with a non-fixed input/output ratio is realized. Additionally, two acceleration strategies for ILP, scheduling constraint reduction and upper boundary estimation of fluidic port number, are proposed to improve the efficiency of SlimPort. Experimental results from multiple benchmarks demonstrate that SlimPort leads to high assay execution efficiency and a low number of fluidic ports. © 2025 by the authors.
Keyword ：
Biochips Biochips Fluidic logic devices Fluidic logic devices High level synthesis High level synthesis Integer linear programming Integer linear programming Integer programming Integer programming Linear programming Linear programming Microfluidic chips Microfluidic chips
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Pan, Youlin , Xu, Yanbo , Chen, Ziyang et al. SlimPort: Port-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips [J]. | Micromachines , 2025 , 16 (5) . |
| MLA | Pan, Youlin et al. "SlimPort: Port-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips" . | Micromachines 16 . 5 (2025) . |
| APA | Pan, Youlin , Xu, Yanbo , Chen, Ziyang , Huang, Xing , Liu, Genggeng . SlimPort: Port-Driven High-Level Synthesis for Continuous-Flow Microfluidic Biochips . | Micromachines , 2025 , 16 (5) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
The high frequency characteristics of rapid single-flux-quantum (RSFQ) circuits poses a great challenge to circuit layout design. In order to solve the circuit delay problem caused by the high frequency characteristics of RSFQ, delay elements such as passive transmission line can be used in the routing stage. The delay of a passive transmission line is roughly proportional to its length, and the power consumption of the passive transmission line does not increase with the increase of the wirelength, so length matching routing is a crucial problem for RSFQ circuits. Therefore, we propose an efficient RSFQ circuit routing algorithm considering length matching, including the following key strategies: 1) when generating the initial path, a method of detour routing is presented to meet the partial length matching of passive transmission lines without changing the initial routing space; 2) an iterative resource insertion algorithm based on region-awareness is utilized to reduce the area of additional resources needed to be added; 3) a length-matching driven routing algorithm considering blocking cost is designed, which improves the resource utilization of routing space. Experimental results show that, compared with existing multi-terminal routing algorithms, the proposed algorithm reduces the area required for routing by 8% and the running time by 36%, thus achieving fast and high-quality routing results. © 2025 Science Press. All rights reserved.
Keyword ：
Electric delay lines Electric delay lines Routing algorithms Routing algorithms Routing protocols Routing protocols
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Liu, Genggeng , Yu, Yantao , Zhou, Ruping et al. Rapid Single-Flux-Quantum Circuit Routing Algorithm Considering Length Matching [J]. | Computer Research and Development , 2025 , 62 (5) : 1151-1163 . |
| MLA | Liu, Genggeng et al. "Rapid Single-Flux-Quantum Circuit Routing Algorithm Considering Length Matching" . | Computer Research and Development 62 . 5 (2025) : 1151-1163 . |
| APA | Liu, Genggeng , Yu, Yantao , Zhou, Ruping , Wei, Rongshan , Xu, Ning . Rapid Single-Flux-Quantum Circuit Routing Algorithm Considering Length Matching . | Computer Research and Development , 2025 , 62 (5) , 1151-1163 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Export
| Results： |
Selected to |
| Format： |
