Query：
学者姓名：李凡阳
Refining：
Year
Type
Indexed by
Source
Complex
Co-
Language
Clean All
Abstract ：
This paper proposes a low-noise high-voltage rail-to-rail operational amplifier based on BCD process. For the protection of low-voltage devices in input stage, this paper proposes a common-mode voltage following circuit which not only realizes the stable performance of low-voltage input devices but also improves the gain under full supply voltage. In order to improve the response speed of large signals, this paper proposes a dynamic slew-rate enhancement technology to achieve the characteristics of low quiescent current and large slew-rate. Besides, this paper optimized the low-frequency noise of the proposed architecture. The circuit uses 180nmBCD process, and the simulation results show that after applying the above technology, the supply voltage range is 3.5-36 V, the quiescent current is about 0.99 mA, the equivalent input noise is 0.82 uVp-p, the slew-rate is 15.2 V/us, the setting time is 0.66 us and the open loop gain is 135 dB in full supply voltage range.
Keyword ：
input stage protection input stage protection operational amplifier operational amplifier slew-rate enhancement slew-rate enhancement
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Pan, Jie , Li, Fanyang , Yuan, Yidong et al. A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement [J]. | 2024 27TH INTERNATIONAL SYMPOSIUM ON DESIGN & DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS, DDECS , 2024 : 41-46 . |
| MLA | Pan, Jie et al. "A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement" . | 2024 27TH INTERNATIONAL SYMPOSIUM ON DESIGN & DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS, DDECS (2024) : 41-46 . |
| APA | Pan, Jie , Li, Fanyang , Yuan, Yidong , Zhao, Tianting , Shen, Hongwei , Wen, Liguo et al. A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement . | 2024 27TH INTERNATIONAL SYMPOSIUM ON DESIGN & DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS, DDECS , 2024 , 41-46 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
针对远程医疗中心电信号数据的安全传输问题，提出并设计实现了一种结合心电信号数据特征的SM4加密算法方案。该方案通过对心电信号数据的分析并结合心电信号数据的特征修改SM4加密算法结构，并使用现场可编程门阵列（FPGA）对所提出的心电信号安全传输算法进行硬件电路实现。实验结果表明，该方案在实现心电信号数据安全传输的同时也确保了加密系统能高速实时的进行数据处理。
Keyword ：
FPGA FPGA SM4加密算法 SM4加密算法 安全传输 安全传输 心电信号 心电信号
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 雷晓华 , 李凡阳 . 基于FPGA的心电信号加密算法研究 [J]. | 中国仪器仪表 , 2023 , 6 (04) : 37-42 . |
| MLA | 雷晓华 et al. "基于FPGA的心电信号加密算法研究" . | 中国仪器仪表 6 . 04 (2023) : 37-42 . |
| APA | 雷晓华 , 李凡阳 . 基于FPGA的心电信号加密算法研究 . | 中国仪器仪表 , 2023 , 6 (04) , 37-42 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based Delta sigma modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below -55 dB, and power dissipation is within 57 mu W.
Keyword ：
Delta sigma modulator Delta sigma modulator microphone readout microphone readout VCO VCO
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Li, Fanyang , Yin, Tao , Wu, Shuwen et al. A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique [J]. | ELECTRONICS , 2023 , 12 (24) . |
| MLA | Li, Fanyang et al. "A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique" . | ELECTRONICS 12 . 24 (2023) . |
| APA | Li, Fanyang , Yin, Tao , Wu, Shuwen , Deng, Wenren . A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique . | ELECTRONICS , 2023 , 12 (24) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
In this paper, a type-I phase-locked loop (PLL) is proposed. Compared with the conventional PLL based on an active-RC filter, the lock time is able to be optimized by means of replacing it with a wide-bandwidth PLL-like time-to-analog convertor (TAC) in the proposed PLL. To demonstrate the efficiency of the structure, the proposed PLL is simulated with SMIC 180nm standard CMOS process, achieving the lock time is less than 3μs and the reference spur is less than -51dB, which consumes 3.8 mW under 1.2 V power supply and the core layout area of the PLL is about 0.13mm2. © 2022 IEEE.
Keyword ：
Bandwidth Bandwidth Digital to analog conversion Digital to analog conversion Locks (fasteners) Locks (fasteners) Phase locked loops Phase locked loops
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Li, Fanyang , Zhang, Yanqing , Huang, Gaowen . A lock time improved type-I PLL using a wide-bandwidth PLL-like time domain digital-to-analog convertor [C] . 2022 . |
| MLA | Li, Fanyang et al. "A lock time improved type-I PLL using a wide-bandwidth PLL-like time domain digital-to-analog convertor" . (2022) . |
| APA | Li, Fanyang , Zhang, Yanqing , Huang, Gaowen . A lock time improved type-I PLL using a wide-bandwidth PLL-like time domain digital-to-analog convertor . (2022) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
提出了一种应用于低场核磁共振的采用混合信号传输的读出电路.该读出电路系统主要由前端放大器、接收机与后端模数转换器组成.提出的混合信号传输技术的本质在于利用相位域与电压域的混合模式检测,以及放大器与模数转换器之间的增益分配来增强线性度.采用0.18 μm CMOS工艺设计,仿真结果表明,在1.2 V的电源电压下,整体电路的功耗为0.5 mW,前端放大器的输入1 dB压缩点与ⅡP3分别为-9.31 dBm和-5.98 dBm,接收机的等效输入噪声仅为 2 nV·Hz-1/2.
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 李凡阳 , 郑鹏青 . 一种混合信号传输的低场核磁共振读出电路 [J]. | 微电子学 , 2021 , 51 (4) : 522-526 . |
| MLA | 李凡阳 et al. "一种混合信号传输的低场核磁共振读出电路" . | 微电子学 51 . 4 (2021) : 522-526 . |
| APA | 李凡阳 , 郑鹏青 . 一种混合信号传输的低场核磁共振读出电路 . | 微电子学 , 2021 , 51 (4) , 522-526 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
本发明涉及一种锁相环电路。包括饱和鉴频鉴相器、电荷泵、电流控制振荡器、反相器链、采样保持电路、电压控振荡器、分频器。饱和鉴频鉴相器与电荷泵连接，将输入信号和反馈信号的相位差转换成脉冲电流。锁相环内部包含的伪锁相环将电流脉冲转换成脉宽调制信号。提取脉宽调制信号，将其转换成直流电压信号，该信号进而调制压控振荡器。本发明在减小杂散水平的同时，还实现了快速锁定的功能。
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 李凡阳 , 黄高文 . 一种锁相环电路 : CN202110428576.8[P]. | 2021-04-21 . |
| MLA | 李凡阳 et al. "一种锁相环电路" : CN202110428576.8. | 2021-04-21 . |
| APA | 李凡阳 , 黄高文 . 一种锁相环电路 : CN202110428576.8. | 2021-04-21 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
This paper presents an output offset minimized capacitance-to-digital interface for a MEMS accelerometer. With a gain-enhanced voltage-controlled oscillator (VCO)-based quantization loop, the interface is able to output a digital signal with improved dynamic range. For optimizing the output offset caused by nonideal factors (e.g., the bond-wire drift), a nested digital chopping feedback loop is embedded in the VCO-based quantization loop. It enables the interface to minimize the output offset without digital filtering and digital-to-analog conversion. The proposed architecture is well suited for dynamic range and offset improvements with low cost. Fabricated with a 0.18 mu m Global Foundry (GF) CMOS process, the interface offers a 78 dB dynamic range with 0.4% nonlinearity from a single 2 V supply. With the input referred offset up to 1.3 pF, the offset cancellation loop keeps the DC output offset within 40 mV. The power dissipation is 6.5 mW with a bandwidth of 4 kHz.
Keyword ：
accelerometer accelerometer bond-wire bond-wire digital chopping digital chopping MEMS MEMS offset offset VCO VCO
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Li, Fanyang , Yin, Tao , Yang, Haigang . A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops [J]. | SENSORS , 2021 , 21 (14) . |
| MLA | Li, Fanyang et al. "A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops" . | SENSORS 21 . 14 (2021) . |
| APA | Li, Fanyang , Yin, Tao , Yang, Haigang . A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops . | SENSORS , 2021 , 21 (14) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
An accuracy-improved and internal regulator-free temperature on-chip sensor is proposed. The proposed sensor outputs an accuracy-enhanced pulse width modulation (PWM) signal with a nonlinear current mode feedback pseudo-PLL (Phase-Locked Loop). The pseudo-PLL is able to greatly mitigate the nonlinearity caused by process parameters (eg. threshold voltage and mobility of MOS transistor) without careful compensation. Furthermore, to optimize the area and power supply rejection without an internal regulator, a current mode input and feedback approach in the pseudo-PLL is also presented. The proposed sensor is fabricated with 0.18 mu m standard CMOS process. The measurement results show that the power consumption of the sensor is only 2 mu W under 1.2V supply voltage. With the supply voltage varying within 1 similar to 1.2V, the temperature detection error is maintained within +/-0.2 degrees C in the range of -20 degrees C to 100 degrees C. And the corresponding power supply rejection (PSR) ratio and resolution achieve about 0.15 degrees C/100mV and 0.12 degrees C, respectively.
Keyword ：
current mode current mode low power low power Mathematical model Mathematical model MOSFET MOSFET Oscillators Oscillators Power supplies Power supplies Regulators Regulators Temperature sensor Temperature sensor Temperature sensors Temperature sensors
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Li, Fanyang , Cheng, Shuying . An Accuracy-Improved and Internal Regulator-Free Temperature Sensor With a Non-Linear Current Mode Feedback Pseudo-PLL [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 2021 , 68 (4) : 1138-1142 . |
| MLA | Li, Fanyang et al. "An Accuracy-Improved and Internal Regulator-Free Temperature Sensor With a Non-Linear Current Mode Feedback Pseudo-PLL" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 68 . 4 (2021) : 1138-1142 . |
| APA | Li, Fanyang , Cheng, Shuying . An Accuracy-Improved and Internal Regulator-Free Temperature Sensor With a Non-Linear Current Mode Feedback Pseudo-PLL . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 2021 , 68 (4) , 1138-1142 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
A driving amplifier capable of operating at a minimum voltage is proposed, aiming to subdue the distortion effect caused by large amplitude driving at the hearing aid loudspeaker. Since the linearity of a cascode amplifier usually degrades with the reduced supply voltage, a three-stage cascade amplifier having a parallel cascade second stage, and a folded cascade Class-AB output current control in place are designed. With such an arrangement, the open loop gain should still be maintained at a sufficiently high level even in the presence of increased output amplitude. Also, the minimum supply voltage required can then be reduced to merely vertical bar V-GS vertical bar+2 vertical bar Vd(sat)vertical bar. Fabricated on a 0.18 mu m complementary metal oxide semiconductor (CMOS) process, the proposed amplifier achieves -72dB total harmonic distortion (THD)+noise(N) with a loudspeaker load of 100ohm while operating from a 1.2V supply and being subject to a 1kHz sinusoidal input.
Keyword ：
class-AB class-AB current control current control Driving amplifier Driving amplifier
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Li, Fanyang , Yang, Tao . A Minimum-Voltage Driving Amplifier with Adaptive Three-Stage Open-Loop Gain and Folded Cascade Class-AB Output Current Control [J]. | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS , 2021 , 30 (08) . |
| MLA | Li, Fanyang et al. "A Minimum-Voltage Driving Amplifier with Adaptive Three-Stage Open-Loop Gain and Folded Cascade Class-AB Output Current Control" . | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 30 . 08 (2021) . |
| APA | Li, Fanyang , Yang, Tao . A Minimum-Voltage Driving Amplifier with Adaptive Three-Stage Open-Loop Gain and Folded Cascade Class-AB Output Current Control . | JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS , 2021 , 30 (08) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
采用0.18 μm CMOS工艺,设计了一种基于VCO量化的电容式MEMS加速度计接口电路.电路基于VCO实现量化,可直接输出数字信号,克服了传统模拟力反馈的非线性问题,且不需要ADC或额外的比较器电路,大大降低了电路的复杂性.仿真结果表明,该接口电路系统噪声基底为18 μg·Hz-1/2,最大非线性误差为0.57％,电路功耗为6.7 mW,输入带宽和检测范围分别为2.5 kHz和±1.0g.该接口电路达到较好的性能.
Keyword ：
MEMS MEMS VCO VCO 加速度计 加速度计 接口电路 接口电路
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 李凡阳 , 洪思鑫 . 一种基于VCO量化的MEMS加速度计接口电路 [J]. | 微电子学 , 2020 , 50 (3) : 357-360 . |
| MLA | 李凡阳 et al. "一种基于VCO量化的MEMS加速度计接口电路" . | 微电子学 50 . 3 (2020) : 357-360 . |
| APA | 李凡阳 , 洪思鑫 . 一种基于VCO量化的MEMS加速度计接口电路 . | 微电子学 , 2020 , 50 (3) , 357-360 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Export
| Results： |
Selected to |
| Format： |
