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学者姓名：黄继伟
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为改善振荡器相位噪声性能，设计了一种带有尾电流源反馈的薄膜体声波谐振器（FBAR）振荡器。研究表明，尾电流源晶体管闪烁噪声和谐振回路是振荡器相位噪声的主要来源。为了降低尾电流源晶体管闪烁噪声对振荡器相位噪声的影响，采用两组对称分离且工作在亚阈值区域的P型金属氧化物半导体（PMOS）偏置电流源进行尾电流反馈。与传统单个尾电流源相比，该技术具有更好的相位噪声性能。同时，基于对Hajimiri噪声模型的分析，利用尾电流源反馈技术，控制振荡器在振幅达到峰值及零穿越点时的电流大小，以进一步改善相位噪声性能。高Q值谐振器可以显著提高振荡器的整体相位噪声性能，因此，设计采用高Q值微机电系统（MEMS）器件FBAR作为谐振腔，并通过TSMC 180 nm RF CMOS工艺完成电路设计。结果表明：该振荡器输出频率为1.93GHz，整体电路功耗为580μW，在1 kHz偏频处相位噪声为-89.7 dBc/Hz，计算得到灵敏值（Factor Of Merit, FOM）为217 dB。
Keyword ：
尾电流源反馈 尾电流源反馈 振荡器 振荡器 相位噪声 相位噪声 薄膜体声波谐振器(FBAR) 薄膜体声波谐振器(FBAR)
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| GB/T 7714 | 丁增辉 , 黄继伟 . 一种带有尾电流源反馈的FBAR振荡器 [J]. | 微电子学与计算机 , 2024 , (01) : 113-117 . |
| MLA | 丁增辉 等. "一种带有尾电流源反馈的FBAR振荡器" . | 微电子学与计算机 01 (2024) : 113-117 . |
| APA | 丁增辉 , 黄继伟 . 一种带有尾电流源反馈的FBAR振荡器 . | 微电子学与计算机 , 2024 , (01) , 113-117 . |
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A broadband and CMOS-compatible polarization beam splitter and rotator (PSR) built on the silicon nitride -on-silicon multilayer platform is presented. The PSR is realized by cascading a polarization beam splitter and a polarization rotator, which are both subtly constructed with an asymmetrical directional coupler waveguide struc-ture. The advantage of this device is that the function of PSR can be directly realized in the SiN layer, providing a promising solution to the polarization diversity schemes in SiN photonic circuits. The chip is expected to have high power handling capability as the light is input from the SiN waveguide. The use of silicon dioxide as the upper cladding of the device ensures its compatibility with the metal back-end-of-line process. By optimizing the struc-ture parameters, a polarization conversion loss lower than 1 dB and cross talk larger than 27.6 dB can be obtained for TM-TE mode conversion over a wavelength range of 1450 to 1600 nm. For TE mode, the insertion loss is lower than 0.26 dB and cross talk is larger than 25.3 dB over the same wavelength range. The proposed device has good potential in diversifying the functionalities of the multilayer photonic chip with high integration density.(c) 2023 Optica Publishing Group
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| GB/T 7714 | Wang, Linghua , Peng, Hejie , Zheng, Langteng et al. Broadband and CMOS-compatible polarization splitter and rotator built on a silicon nitride-on-silicon multilayer platform [J]. | APPLIED OPTICS , 2023 , 62 (4) : 1046-1056 . |
| MLA | Wang, Linghua et al. "Broadband and CMOS-compatible polarization splitter and rotator built on a silicon nitride-on-silicon multilayer platform" . | APPLIED OPTICS 62 . 4 (2023) : 1046-1056 . |
| APA | Wang, Linghua , Peng, Hejie , Zheng, Langteng , Chen, Huaixi , Zhang, Yazhen , Huang, Jiwei et al. Broadband and CMOS-compatible polarization splitter and rotator built on a silicon nitride-on-silicon multilayer platform . | APPLIED OPTICS , 2023 , 62 (4) , 1046-1056 . |
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A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8-511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz. © Published under licence by IOP Publishing Ltd.
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| GB/T 7714 | Zhao, M. , Huang, J. . Design of a multi-modulus divider with a wide frequency dividing range and low power consumption [未知]. |
| MLA | Zhao, M. et al. "Design of a multi-modulus divider with a wide frequency dividing range and low power consumption" [未知]. |
| APA | Zhao, M. , Huang, J. . Design of a multi-modulus divider with a wide frequency dividing range and low power consumption [未知]. |
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Wireless receivers with multiple modes and standards require highly linear Pre-filters to prevent strong out-of-band blocker signals from corrupting in-band signals. A prefaced SAW(surface acoustic wave) filter needed in conventional receiver structures is neither tunable nor fully integrated. However, when the multiple frequency bands demand to be supported, the combination of multiple SAW filters increases the circuit's size and cost. This paper introduces a fully integrated, reconfigurable wideband wireless receiver based on N-path technology. The circuit utilizes 65nm CMOS technology and applies the Gain-Boosted approach to reduce the noise factor to 3.3dB. The out-of-band suppression ability of the circuit is improved by N-path technology, and the out-of-band IIP3 is up to +33.51dBm. The circuit's power consumes 46-72mW at 0.5-2GHz frequency, and the layout area is 700∗1000μm2 © 2023 ACM.
Keyword ：
Bandpass Bandpass Blocker-Tolerant Blocker-Tolerant CMOS CMOS high linearity high linearity N-path N-path OOB-IIP3 OOB-IIP3 passive mixer passive mixer surface acoustic wave (SAW) less surface acoustic wave (SAW) less
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| GB/T 7714 | Wu, W. , Huang, J. , Wu, R. et al. A High-Linearity CMOS Receiver based on N-path Technology in Wideband Operation [未知]. |
| MLA | Wu, W. et al. "A High-Linearity CMOS Receiver based on N-path Technology in Wideband Operation" [未知]. |
| APA | Wu, W. , Huang, J. , Wu, R. , Shi, J. . A High-Linearity CMOS Receiver based on N-path Technology in Wideband Operation [未知]. |
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This paper presents a high-precision, low-power CMOS temperature-to-digital converter (TDC) for detecting MEMS reference fre-quency sources on-chip temperature. This TDC uses a bipolar transistor as the core device for temperature measurement and a second-order Sigma -Delta ADC to read the temperature information. In order to improve the accuracy, the PTAT bias circuit with finite current gain compensation re-sistor and Dynamic Element Matching (DEM) circuit with Bank-Swap structure is employed in the temperature front-end circuit, respectively. In the ADC design, Analog T-switches (AT-Switch) with complementary structures are employed to reduce the leakage current of MOS switches in a fully differential switched-capacitor integrator to improve the accu-racy further. Implemented in TSMC 180 nm CMOS, the TDC occupies 0.135 mm2. The measurement results show that the average power con-sumption of the circuit is 95 mu W (@27 degrees C) at a supply voltage of 1.8 V. After temperature curve fitting, an inaccuracy of +/- 0.85 degrees C (3 sigma) is achieved from -40 degrees C to 85 degrees C, which meets the requirements of the FBAR (Flim Bulk Acoustic-wave Resonator) oscillator for temperature compensation.
Keyword ：
AT-switch AT-switch BJT-based BJT-based dynamic element matching (DEM) dynamic element matching (DEM) sigma-delta ADC sigma-delta ADC temperature sensor temperature sensor
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| GB/T 7714 | Huang, Jiwei , Zheng, Xiaodong , Guo, Xiaojie et al. A high precision CMOS temperature sensor for MEMS oscillator [J]. | IEICE ELECTRONICS EXPRESS , 2023 , 20 (24) . |
| MLA | Huang, Jiwei et al. "A high precision CMOS temperature sensor for MEMS oscillator" . | IEICE ELECTRONICS EXPRESS 20 . 24 (2023) . |
| APA | Huang, Jiwei , Zheng, Xiaodong , Guo, Xiaojie , Jin, Jing , Liu, Haoyu . A high precision CMOS temperature sensor for MEMS oscillator . | IEICE ELECTRONICS EXPRESS , 2023 , 20 (24) . |
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In this paper, a low voltage and low power charge pump PLL based on current-reuse LC oscillator is designed. Different from the traditional differential LC VCO, the VCO in this design uses the cross-coupled pair of PMOS and NMOS to achieve the effect of Current-Reuse. The phase noise of the VCO is not affected by the second harmonic term of the common source node. In order to further reduce power consumption, the design uses 0.8V low voltage power supply and all the MOSFETs adopt a low threshold structure. The simulation results show that the power consumption of the whole circuit is 1.2mW and the phase noise at 1MHz frequency offset is -109dBc/Hz when the PLL output is 1.8GHz under the TSMC 180nm process and 0.8V supply voltage. The whole PLL can achieve integer frequency division of 1.68GHz ∼ 1.92 GHz, and the locking time is less than 10us. © 2023 IEEE.
Keyword ：
Electric power utilization Electric power utilization Frequency allocation Frequency allocation Phase locked loops Phase locked loops Phase noise Phase noise Variable frequency oscillators Variable frequency oscillators
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| GB/T 7714 | Zheng, Yifeng , Wu, Runsen , Huang, Jiwei . Low Voltage and Low Power PLL with Current-Reuse Oscillator [C] . 2023 : 448-451 . |
| MLA | Zheng, Yifeng et al. "Low Voltage and Low Power PLL with Current-Reuse Oscillator" . (2023) : 448-451 . |
| APA | Zheng, Yifeng , Wu, Runsen , Huang, Jiwei . Low Voltage and Low Power PLL with Current-Reuse Oscillator . (2023) : 448-451 . |
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本文设计了 一种具有低静态电流的低压差线性稳压器(LDO).针对传统LDO在低静态电流下瞬态响应不足的问题,电路中的误差放大器采用两个共栅差分跨导单元交叉耦合连接进行设计,提高其压摆率;利用体偏置运放改变功率管的阈值电压实现功率管在不同负载的快速切换;同时采用动态偏置对电路进行偏置减少过欠冲值.电路采用台积电(TSMC)0.18 μm互补金属氧化物半导体(CMOS)工艺进行设计,版图核心面积为220 μm×140 μm.仿真结果表明,该LDO在最小负载电流与最大负载电容的组合下相位裕度达到100度,消耗的静态电流仅为849 nA.当负载电流在500 ns时间内从100 μA到100 mA进行切换时,电路表现出良好的瞬态响应,其中过冲电压为220 mV,欠冲电压为225 mV.经过计算,品质因数(FOM)值为0.198 mV.
Keyword ：
FOM FOM 低压差线性稳压器 低压差线性稳压器 低静态电流 低静态电流 体偏置运放 体偏置运放 共栅差分跨导单元 共栅差分跨导单元 动态偏置 动态偏置
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| GB/T 7714 | 吴为清 , 黄继伟 . 基于高摆率误差放大器的低功耗LDO设计 [J]. | 微电子学与计算机 , 2023 , 40 (12) : 81-86 . |
| MLA | 吴为清 et al. "基于高摆率误差放大器的低功耗LDO设计" . | 微电子学与计算机 40 . 12 (2023) : 81-86 . |
| APA | 吴为清 , 黄继伟 . 基于高摆率误差放大器的低功耗LDO设计 . | 微电子学与计算机 , 2023 , 40 (12) , 81-86 . |
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本发明公开了一种应用于ADC的低功耗高瞬态LDO，采用改进型源输入共栅极放大器以解决低静态电流下误差放大器的摆率不足的问题，利用体偏置放大器让功率管更快进入饱和区，以及采用动态偏置提高整体电路的瞬态特性。整体电路分为改进型误差放大器、动态偏置电路、体偏置电路与保护模块四个模块。该结构为低功耗ADC提供稳定的电源电压。该结构消耗nA级静态功耗，满足低功耗的要求。
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| GB/T 7714 | 黄继伟 , 吴为清 , 金靖 et al. 应用于ADC的低功耗高瞬态LDO : CN202211108126.1[P]. | 2022-09-13 00:00:00 . |
| MLA | 黄继伟 et al. "应用于ADC的低功耗高瞬态LDO" : CN202211108126.1. | 2022-09-13 00:00:00 . |
| APA | 黄继伟 , 吴为清 , 金靖 , 刘皓宇 , 郭屹粟 . 应用于ADC的低功耗高瞬态LDO : CN202211108126.1. | 2022-09-13 00:00:00 . |
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本实用新型公开了一种预失真负反馈驱动放大器的偏置模块电路，包括：相连接的：电流镜电路和相位补偿电路；所述电流镜电路包括由三极管QB1‑QB3以及三极管Q0构成电流镜；其中，三极管QB1的发射极经电阻R0接地，集电极和基极接三极管QB3的发射极；所述三极管QB3的集电极和基极与三极管QB2的基极经一电容接地，并经电阻R2接电压输入端Vref1；所述三极管QB2的集电极接电压输入端VCC，且发射极经相位补偿电路和电阻R1接三极管Q0的基极，并经一电容接入输入信号；所述三极管Q0的发射极接地，集电极经一电感接电压输入端VCC且经一电容接地，并作为信号输出端；所述相位补偿电路用于形成反向电容Cbc‑rb以抵消三极管Q0的基极‑集电极寄生电容Cbc。
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| GB/T 7714 | 黄继伟 , 龚著浩 , 倪栋梁 et al. 预失真负反馈驱动放大器的偏置模块电路 : CN202222423255.1[P]. | 2022-09-14 00:00:00 . |
| MLA | 黄继伟 et al. "预失真负反馈驱动放大器的偏置模块电路" : CN202222423255.1. | 2022-09-14 00:00:00 . |
| APA | 黄继伟 , 龚著浩 , 倪栋梁 , 李梁锋 , 吴维嘉 . 预失真负反馈驱动放大器的偏置模块电路 : CN202222423255.1. | 2022-09-14 00:00:00 . |
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In this paper, a reconfigurable 10/20/40/80 MHz bandwidth Butterworth active-RC low-pass filter (LPF) in 55 nm CMOS for IEEE 802.11ax receiver is presented. This filter has a programmable in-band gain, which can save additional amplifier circuits and reduce analog baseband power consumption. Programmable capacitor array of the filter is used to adjust bandwidth. Adjust the gain ranging from 0 to 24 dB in-band by programmable resistor array. The prototype filter consumes a current 25.1 mA at 1.5 V supply and occupies 0.084 mm2. The spurious free dynamic range (SFDR) of the LPF reaches 71 dB, and the NF is less than 35 dB over the filter's bandwidth. © 2023 IEEE.
Keyword ：
Bandwidth Bandwidth Butterworth filters Butterworth filters IEEE Standards IEEE Standards Low pass filters Low pass filters Passive filters Passive filters Timing circuits Timing circuits Wireless local area networks (WLAN) Wireless local area networks (WLAN)
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| GB/T 7714 | Wang, Wenzhen , Huang, Jiwei . A 10/20/40/80 MHz 3rd-order Active-RC Butterworth LPF for 802.11ax Receiver [C] . 2023 : 676-680 . |
| MLA | Wang, Wenzhen et al. "A 10/20/40/80 MHz 3rd-order Active-RC Butterworth LPF for 802.11ax Receiver" . (2023) : 676-680 . |
| APA | Wang, Wenzhen , Huang, Jiwei . A 10/20/40/80 MHz 3rd-order Active-RC Butterworth LPF for 802.11ax Receiver . (2023) : 676-680 . |
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