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学者姓名：胡炜
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Traditionally, the precision of noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) is limited by the linearity of open-loop residue amplifier and it is challenging to achieve high-order (>= 3) noise-shaping. To mitigate aforementioned limitations, we innovatively propose a fourth-order NS SAR ADC, which adopts the 2-2 hybrid nested (HN) structure that nests error feedback (EF) and cascaded integrator feed-forward (CIFF). With the aid of the 2-2 HN structure, a process-voltage-temperature (PVT)-robust high-order noise-shaping has been successfully implemented in NS SAR ADC. Moreover, to achieve high precision: (1) The closed-loop cascode floating inverter amplifier (FIA) is employed as residue amplifier, breaking the tradeoff between linearity of dynamic amplifier and high precision while maintaining high power efficiency, and realizing a truly high-precision NS SAR ADC with PVT robustness. (2) Sampling KT/C noise cancellation (SNC) technique is exploited to reduce the size of capacitive digital-to-analog converter (CDAC) while meeting the same precision requirements. The proposed ADC was prototyped in a 55 nm CMOS process, achieving a high-precision signal-to-noise-and-distortion ratio (SNDR) of 92.6 dB, capable of maintaining SNDR exceeding 90 dB across PVT variations. It operates within a 312.5 kHz bandwidth (BW) with an oversampling ratio (OSR) of 8, consuming 272 mu W power under 1.2 V supply and realizing a Schreier figure of merit (FoMs) of 183 dB.
Keyword ：
Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) Floating inverter amplifier Floating inverter amplifier Noise cancellation Noise cancellation Noise shaping (NS) Noise shaping (NS) Successive approximation register (SAR) Successive approximation register (SAR)
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| GB/T 7714 | Hu, Wei , Li, Jiaqi , Chen, Qunchao . A 92 dB SNDR 183 dB FoMs Fully Dynamic Fourth-Order Noise-Shaping SAR ADC in the 2-2 Hybrid Nested Structure with Closed-Loop Residue Amplifier [J]. | CIRCUITS SYSTEMS AND SIGNAL PROCESSING , 2025 , 44 (6) : 3697-3713 . |
| MLA | Hu, Wei 等. "A 92 dB SNDR 183 dB FoMs Fully Dynamic Fourth-Order Noise-Shaping SAR ADC in the 2-2 Hybrid Nested Structure with Closed-Loop Residue Amplifier" . | CIRCUITS SYSTEMS AND SIGNAL PROCESSING 44 . 6 (2025) : 3697-3713 . |
| APA | Hu, Wei , Li, Jiaqi , Chen, Qunchao . A 92 dB SNDR 183 dB FoMs Fully Dynamic Fourth-Order Noise-Shaping SAR ADC in the 2-2 Hybrid Nested Structure with Closed-Loop Residue Amplifier . | CIRCUITS SYSTEMS AND SIGNAL PROCESSING , 2025 , 44 (6) , 3697-3713 . |
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The next-generation computing system is required to perform 10(18) floating point operations per second to address the exponential growth of data from sensory terminals, driven by advancements in artificial intelligence and the Internet of Things. Even if a supercomputer possesses the capability to execute these operations, managing heat dissipation becomes a significant challenge when the electronic synapse array reaches a comparable scale with the human neuron network. One potential solution to address thermal hotspots in electronic devices is the use of vertically-aligned hexagonal boron nitride (h-BN) known for its high thermal conductivity. In this study, we have developed textured h-BN films using the high power impulse magnetron sputtering technique. The thermal conductivity of the oriented h-BN film is approximately 354% higher than that of the randomly oriented counterpart. By fabricating electronic synapses based on the textured h-BN thin film, we demonstrate various bio-synaptic plasticity in this device. Our results indicate that orientation engineering can effectively enable h-BN to function as a suitable self-heat dissipation layer, thereby paving the way for future wearable memory devices, solar cells, and neuromorphic devices.
Keyword ：
boron nitride boron nitride high thermal conductivity high thermal conductivity low-power memory low-power memory neuromorphic computing neuromorphic computing vertically-aligned vertically-aligned
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| GB/T 7714 | Zhang, Haizhong , Ju, Xin , Jiang, Haitao et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor [J]. | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) : 1907-1914 . |
| MLA | Zhang, Haizhong et al. "Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor" . | SCIENCE CHINA-MATERIALS 67 . 6 (2024) : 1907-1914 . |
| APA | Zhang, Haizhong , Ju, Xin , Jiang, Haitao , Yang, Dan , Wei, Rongshan , Hu, Wei et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor . | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) , 1907-1914 . |
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Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings.
Keyword ：
computing-in-memory computing-in-memory low latency low latency RRAM RRAM voltage sense amplifier voltage sense amplifier
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| GB/T 7714 | Hu, Wei , Zhang, Hangze , Wei, Rongshan et al. A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits [J]. | ELECTRONICS , 2024 , 13 (2) . |
| MLA | Hu, Wei et al. "A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits" . | ELECTRONICS 13 . 2 (2024) . |
| APA | Hu, Wei , Zhang, Hangze , Wei, Rongshan , Chen, Qunchao . A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits . | ELECTRONICS , 2024 , 13 (2) . |
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电流反馈仪表放大器芯片因其高精度、高共模抑制比等优势,广泛应用于微弱信号检测.传统CFIA利用斩波技术降低 1/f 噪声和失调电压以提升放大器精度,但额外引入斩波波纹会显著限制其精度提升.为此,本文提出一种基于自适应时钟和波纹减小环路的新型电流反馈仪表放大器ARCFIA,该放大器针对传统斩波放大器波纹,采用波纹减少环路RRL对其抑制,并借助自适应时钟ACLK,将斩波开关的输入参考噪声谱密度降低.实验结果表明,ARCFIA实现了低于 1.4 μV的低失调电压和 17.2 nV/Hz的输入参考噪声,同时波纹被减少到ARCFIA噪声基底以下,通过减小失调、噪声和波纹,实现了精度的进一步提升.此外,ARCFIA还具有一定潜力应用于复杂环境下的高精度测量系统.
Keyword ：
低噪声 低噪声 低失调 低失调 波纹减少 波纹减少 电流反馈仪表放大器 电流反馈仪表放大器 自适应时钟 自适应时钟 高精度 高精度
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| GB/T 7714 | 胡炜 , 吴展鹏 , 程捷文 et al. 一种基于自适应时钟和波纹减少环路的高精度电流反馈仪表放大器 [J]. | 仪器仪表学报 , 2024 , 45 (8) : 259-267 . |
| MLA | 胡炜 et al. "一种基于自适应时钟和波纹减少环路的高精度电流反馈仪表放大器" . | 仪器仪表学报 45 . 8 (2024) : 259-267 . |
| APA | 胡炜 , 吴展鹏 , 程捷文 , 魏榕山 . 一种基于自适应时钟和波纹减少环路的高精度电流反馈仪表放大器 . | 仪器仪表学报 , 2024 , 45 (8) , 259-267 . |
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组合优化问题（combinatorial optimization problem,COP）是一类在离散空间中寻找最优解的数学问题，具有广泛的应用。然而，许多组合优化问题是NP完全的，随着问题规模的增加，解决问题所需的时间急剧增加，这促使研究人员寻求更快速的解决方法，即使解不一定是最优的，如近似算法、启发式算法和机器学习算法等。一些先前的工作基于Hopfield神经网络提出了混沌模拟退火（chaoticsimulatedannealing,CSA），并取得了良好的表现。然而，CSA的计算模式对当前的通用处理器并不友好，且没有专用的计算硬件。为了高效地执行CSA，我们提出一种软硬件联合的设计方案。在软件方面，我们使用适当的位宽对权重和输出进行量化，并修改那些不适合硬件实现的计算模式。在硬件方面，我们设计了一种基于忆阻器的专用存内计算硬件架构COPPER。COPPER能够高效地运行修改后的量化CSA算法，并支持流水线以获得进一步加速。结果表明，COPPER在执行CSA算法时，速度和能耗方面都十分出色。
Keyword ：
存内计算 存内计算 混沌模拟退火 混沌模拟退火 组合优化问题 组合优化问题
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| GB/T 7714 | 汪乾坤 , 李星辰 , 吴秉哲 et al. COPPER:具有存内计算架构的组合优化问题求解器（英文） [J]. | Frontiers of Information Technology & Electronic Engineering , 2023 , 24 (05) : 731-742 . |
| MLA | 汪乾坤 et al. "COPPER:具有存内计算架构的组合优化问题求解器（英文）" . | Frontiers of Information Technology & Electronic Engineering 24 . 05 (2023) : 731-742 . |
| APA | 汪乾坤 , 李星辰 , 吴秉哲 , 杨可 , 胡炜 , 孙广宇 et al. COPPER:具有存内计算架构的组合优化问题求解器（英文） . | Frontiers of Information Technology & Electronic Engineering , 2023 , 24 (05) , 731-742 . |
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We propose a novel technology called depolarization field engineered ferroelectric mechanical transistor (Fe-MT), which achieves an exceptionally low operating voltage (V-DD) of 0.3 volts. This achievement of VDD scaling is made possible by utilizing depolarization voltage with an amplitude of 11/-11.1 V for the pre-shrinkage of contact gap (g(C)) [Fig. 1], which is activated by a + 63/-66 V pulse stimulus. Additionally, our Fe-MTs maintain the device level reconfigurability between N/P modes. This exciting development suggests that our Fe-MTs can serve as the fundamental building blocks for future generations of integrated circuits with high energy and area-efficiency.
Keyword ：
depolarization field depolarization field Ferroelectric Ferroelectric Ferroelectric devices Ferroelectric devices micro-electro-mechanical (MEM) micro-electro-mechanical (MEM) Micromechanical devices Micromechanical devices operating voltage operating voltage reconfigurability reconfigurability Reconfigurable devices Reconfigurable devices Transistors Transistors Voltage Voltage
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| GB/T 7714 | Cui, Mengkuo , Zhou, Jiuren , Zheng, Siying et al. Depolarization Field Engineered Ferroelectric Mechanical Transistor With 0.3-Volts VDD [J]. | IEEE ELECTRON DEVICE LETTERS , 2023 , 44 (12) : 2063-2066 . |
| MLA | Cui, Mengkuo et al. "Depolarization Field Engineered Ferroelectric Mechanical Transistor With 0.3-Volts VDD" . | IEEE ELECTRON DEVICE LETTERS 44 . 12 (2023) : 2063-2066 . |
| APA | Cui, Mengkuo , Zhou, Jiuren , Zheng, Siying , Liu, Ning , Liang, Jie , Hu, Wei et al. Depolarization Field Engineered Ferroelectric Mechanical Transistor With 0.3-Volts VDD . | IEEE ELECTRON DEVICE LETTERS , 2023 , 44 (12) , 2063-2066 . |
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This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of +/- 0.11 degrees C (3 sigma), exceeding the accuracy of +/- 0.23 degrees C (3 sigma) achieved without calibration. We implement the sensor in a 0.18 mu m CMOS process, occupying an area of 0.42 mm(2). It achieves a resolution of 0.01 degrees C and has a conversion time of 24 ms.
Keyword ：
calibration calibration delta-sigma modulation delta-sigma modulation high precision high precision neural network neural network temperature sensor temperature sensor
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| GB/T 7714 | Wei, Rongshan , Lin, Huishan , Chen, Qunchao et al. A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of +/- 0.11 (3 sigma) [J]. | SENSORS , 2023 , 23 (11) . |
| MLA | Wei, Rongshan et al. "A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of +/- 0.11 (3 sigma)" . | SENSORS 23 . 11 (2023) . |
| APA | Wei, Rongshan , Lin, Huishan , Chen, Qunchao , Huang, Gongxing , Hu, Wei . A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of +/- 0.11 (3 sigma) . | SENSORS , 2023 , 23 (11) . |
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This paper presents a low-power capacitive-to-digital converter (CDC) based on incremental delta-sigma modulator. It utilizes a zoom-in sensing capacitor that is insensitive to parasitic capacitance, improving the capacitance resolution. The use of a high-gain, PVT-robust current-starved OTA and a dynamic bias comparator enhances the efficiency of the system. An ultra-low-power bias circuit is integrated into the system, further improving integration and efficiency. The proposed CDC is fabricated using a 180 nm CMOS process. Operating at a 1.2 V supply voltage and a 250 kHz sampling frequency. With a measurement time of 0.8 ms, the capacitance resolution is 107.6 aF, and the power consumption is 10.27 mu W. The figure-of-merits (FoM) is 2.06 pJ/step.
Keyword ：
Capacitive-to-digital Capacitive-to-digital Current-starved OTA Current-starved OTA Delta-sigma Delta-sigma Low power Low power
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| GB/T 7714 | Wei, Rongshan , Wei, Cong , Huang, Lijie et al. Low power capacitive-to-digital converter based on incremental delta-sigma modulator [J]. | MICROELECTRONICS JOURNAL , 2023 , 142 . |
| MLA | Wei, Rongshan et al. "Low power capacitive-to-digital converter based on incremental delta-sigma modulator" . | MICROELECTRONICS JOURNAL 142 (2023) . |
| APA | Wei, Rongshan , Wei, Cong , Huang, Lijie , Huang, Gongxing , Wang, Renping , Hu, Wei . Low power capacitive-to-digital converter based on incremental delta-sigma modulator . | MICROELECTRONICS JOURNAL , 2023 , 142 . |
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A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA's DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at -30 to 120 degrees C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/degrees C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.
Keyword ：
correlated level shifting correlated level shifting switched-capacitor switched-capacitor voltage reference voltage reference
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| GB/T 7714 | Wei, Rongshan , Chen, Chu , Wei, Cong et al. An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique [J]. | ELECTRONICS , 2023 , 12 (24) . |
| MLA | Wei, Rongshan et al. "An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique" . | ELECTRONICS 12 . 24 (2023) . |
| APA | Wei, Rongshan , Chen, Chu , Wei, Cong , Wang, Renping , Huang, Lijie , Zhou, Qikun et al. An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique . | ELECTRONICS , 2023 , 12 (24) . |
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The combinatorial optimization problem (COP), which aims to find the optimal solution in discrete space, is fundamental in various fields. Unfortunately, many COPs are NP-complete, and require much more time to solve as the problem scale increases. Troubled by this, researchers may prefer fast methods even if they are not exact, so approximation algorithms, heuristic algorithms, and machine learning have been proposed. Some works proposed chaotic simulated annealing (CSA) based on the Hopfield neural network and did a good job. However, CSA is not something that current general-purpose processors can handle easily, and there is no special hardware for it. To efficiently perform CSA, we propose a software and hardware co-design. In software, we quantize the weight and output using appropriate bit widths, and then modify the calculations that are not suitable for hardware implementation. In hardware, we design a specialized processing-in-memory hardware architecture named COPPER based on the memristor. COPPER is capable of efficiently running the modified quantized CSA algorithm and supporting the pipeline further acceleration. The results show that COPPER can perform CSA remarkably well in both speed and energy.
Keyword ：
1 1 Chaotic simulated annealing Chaotic simulated annealing Combinatorial optimization Combinatorial optimization Processing-in-memory Processing-in-memory TP389 TP389
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| GB/T 7714 | Wang, Qiankun , Li, Xingchen , Wu, Bingzhe et al. COPPER: a combinatorial optimization problem solver with processing-in-memory architecture [J]. | FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING , 2023 , 24 (5) : 731-741 . |
| MLA | Wang, Qiankun et al. "COPPER: a combinatorial optimization problem solver with processing-in-memory architecture" . | FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING 24 . 5 (2023) : 731-741 . |
| APA | Wang, Qiankun , Li, Xingchen , Wu, Bingzhe , Yang, Ke , Hu, Wei , Sun, Guangyu et al. COPPER: a combinatorial optimization problem solver with processing-in-memory architecture . | FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING , 2023 , 24 (5) , 731-741 . |
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