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学者姓名：陈传东
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由于不断增长的芯片引脚数量、极高的引脚密度和独特的物理限制，印刷电路板（Printed Circuit Board,PCB）的手动布线已成为一项耗时的任务。近年来，高效率的自动化布线技术得到了广泛的研究。区域布线是PCB设计的一个重要组成部分。针对基于静态网格区域布线的方案，布线拥塞、布通率低等问题，本文提出了一套基于动态网格的135度区域布线算法，主要包括以下技术:（1）对当前布线采用实时扩展动态网格；（2）135度布线角度节点调整算法；（3）基于拥塞控制的改进A~*算法；（4）有效的拆线重布机制。实验结果表明，该算法对于所有工业界布线测试用例布通率都达到100%，并且运行时间方面优于工业布线器Free Routing和Allegro。
Keyword ：
A~*算法 A~*算法 动态网格 动态网格 区域布线 区域布线 拆线重布 拆线重布
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| GB/T 7714 | 陈云梦 , 陈传东 , 陈家瑞 et al. 基于动态网格的135度PCB区域布线算法 [J]. | 中国集成电路 , 2024 , 33 (03) : 19-25,31 . |
| MLA | 陈云梦 et al. "基于动态网格的135度PCB区域布线算法" . | 中国集成电路 33 . 03 (2024) : 19-25,31 . |
| APA | 陈云梦 , 陈传东 , 陈家瑞 , 周宇靖 . 基于动态网格的135度PCB区域布线算法 . | 中国集成电路 , 2024 , 33 (03) , 19-25,31 . |
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Ordered Escape Routing (OER) problem, which is an NP-hard problem, is critical in PCB design. Primary methods based on integer linear programming (ILP) or heuristic algorithms work well on small-scale PCBs with fewer pins. However, when dealing with large-scale instances, the performance of ILP strategies suffers dramatically as the number of variables increases due to time-consuming preprocessing. As for heuristic algorithms, ripping-up and rerouting is adopted to increase resource utilization, which frequently causes time violation. In this paper, we propose an efficient ILP-based routing engine for dense PCB to simultaneously minimize wiring length and runtime, considering the specific routing constraints. By weighting the length, we first model the OER problem as a special network flow problem. Then we separate the non-crossing constraint from typical ILP modeling to reduce the number of integral variables greatly. In addition, considering the congestion of routing resources, the ILP method is proposed to detect congestion. Finally, unlike the traditional schemes that deal with negotiated congestion, our approach works by reducing the local area capacity and then allowing the global automatic optimization of congestion. Compared with the state-of-the-art work, experimental results show that our algorithm can solve cases in larger scale in high routing quality of less length and reduce routing time by 76%.
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| GB/T 7714 | Chen, Chuandong , Lin, Dishi , Wei, Rongshan et al. Efficient Global Optimization for Large Scaled Ordered Escape Routing [J]. | 2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC , 2023 : 535-540 . |
| MLA | Chen, Chuandong et al. "Efficient Global Optimization for Large Scaled Ordered Escape Routing" . | 2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC (2023) : 535-540 . |
| APA | Chen, Chuandong , Lin, Dishi , Wei, Rongshan , Liu, Qinghai , Zhu, Ziran , Chen, Jianli . Efficient Global Optimization for Large Scaled Ordered Escape Routing . | 2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC , 2023 , 535-540 . |
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有序逃逸布线问题作为PCB设计中的关键一环,属于一类特殊的NP-困难问题,近年来得到广泛研究.传统方法中,基于整数线性规划或者是拆线重布类的启发式算法只适用于引脚数目较少的PCB引脚阵列,否则容易出现时间违规而导致布线失败.针对传统方法中大规模全局自动布线难的问题,基于线性规划的全局自动布线算法提出采用线性规划解决逃逸布线问题,并提出降低线网容量化解拥塞的新方法.与最新的逃逸布线算法相比,在处理大规模问题时,该算法不仅可以实现全部引脚的有序逃逸,并且布线时间提升50％,节省31％线长.
Keyword ：
PCB自动布线 PCB自动布线 拥塞驱动 拥塞驱动 有序逃逸 有序逃逸 线性规划 线性规划
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| GB/T 7714 | 陈虹 , 陈传东 , 魏榕山 . 一种基于线性规划的全局逃逸布线算法 [J]. | 电子技术应用 , 2023 , 49 (1) : 97-101 . |
| MLA | 陈虹 et al. "一种基于线性规划的全局逃逸布线算法" . | 电子技术应用 49 . 1 (2023) : 97-101 . |
| APA | 陈虹 , 陈传东 , 魏榕山 . 一种基于线性规划的全局逃逸布线算法 . | 电子技术应用 , 2023 , 49 (1) , 97-101 . |
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Legalized routing is an essential part of PCB automatic routing. It solves the problem of wiring conflicts and obtains routing results that comply with the constraints of design rules. Traditional legalized routing problems mostly use trial backtracking methods, but with increasing design complexity and design rules, avoiding wiring conflicts between networks has become increasingly challenging. This paper proposes a legalized routing algorithm based on linear programming to obtain the optimal wiring trajectory under specified topological constraints. First, the corresponding routing model was established based on numerous routing rules, and a routing grid diagram was found using obstacles as grid points. Secondly, a global routing algorithm was used to obtain the estimated wiring path, and integer linear programming was used to realize the mathematical modeling of the legalized routing problem. Finally, a multi-line simultaneous routing strategy was used to design and implement a detailed routing algorithm, optimizing the routing results. We use C++ to complete the coding work and thoroughly test the PCB use cases of different sizes. The experimental results show that our algorithm still maintains a 100% routing success rate, good time performance, and excellent routing quality with large-scale use cases compared with the trial backtracking method.
Keyword ：
detailed algorithm detailed algorithm escape routing escape routing integer linear programming integer linear programming printed circuit board printed circuit board
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| GB/T 7714 | Chen, Chuandong , Tong, Xin , Liu, Qinghai et al. Legalized Routing Algorithm Based on Linear Programming [J]. | ELECTRONICS , 2023 , 12 (20) . |
| MLA | Chen, Chuandong et al. "Legalized Routing Algorithm Based on Linear Programming" . | ELECTRONICS 12 . 20 (2023) . |
| APA | Chen, Chuandong , Tong, Xin , Liu, Qinghai , Chen, Jiarui , Lin, Zhifeng . Legalized Routing Algorithm Based on Linear Programming . | ELECTRONICS , 2023 , 12 (20) . |
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Abstract ：
Escape routing is a critical problem in PCB routing, and its quality greatly affects the PCB design cost. Unlike the traditional escape routing that works mainly for the BGA package with unique line width and space, this paper presents a high-performance escape routing algorithm to handle problems with variable design rules and manual constraints, including variable line widths/spaces, the neck mode of wires, and the pad entry for differential pairs. We first propose a novel obstacle-avoiding method to project pins to the boundary and construct a channel projection graph. We then construct a bi-projection graph and propose a matching-based hierarchical sequencing algorithm to consider manual constraints. We perform global routing for each pin/differential pair by congestion-avoiding path initialization and rip-up and reroute path optimization. Finally, we complete detailed routing in every face, ensuring the wire angle and pad entry constraints. Experimental results show that our algorithm can achieve 100% routability without any design rule violation for all given industrial PCB instances, while two state-of-the-art routers cannot complete routing.
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| GB/T 7714 | Liu, Qinghai , Lin, Disi , Chen, Chuandong et al. A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints [J]. | IEEE DESIGN AUTOMATION CONFERENCE, DAC , 2023 . |
| MLA | Liu, Qinghai et al. "A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints" . | IEEE DESIGN AUTOMATION CONFERENCE, DAC (2023) . |
| APA | Liu, Qinghai , Lin, Disi , Chen, Chuandong , He, Huan , Chen, Jianli , Chang, Yao-Wen . A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints . | IEEE DESIGN AUTOMATION CONFERENCE, DAC , 2023 . |
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PCB routing becomes time-consuming as the complexity of PCB design increases. Unlike traditional schemes that treat the two essential PCB routing processes separately, namely, escape and bus routing, we consider the continuity between them and present a golden-pin-based routing scheme to find the desired solution with angle and topology constraints. Further, conventional rip-up and reroute methods are often ineffective and inefficient for congestion alleviation and routability optimization. We construct a component graph by modeling components as vertices and applying the minimum weight vertex covering method to improve the routability. A self-adaptable ordering method is presented for escape routing to arrange the pin order on the component boundary, guaranteeing successful bus routing. In addition, escape routing is performed based on a disjoint path method. We construct a dynamic Hanan grid in bus routing and utilize a novel congestion adjustment technique to improve solution quality. Compared with FreeRouting and Allegro, the experiment results show that our algorithm achieves high routability and a significant 90% runtime reduction.
Keyword ：
bus routing bus routing disjoint path disjoint path escape routing escape routing
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| GB/T 7714 | Liu, Qinghai , Tang, Qinfei , Chen, Jiarui et al. Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints [J]. | IEEE DESIGN AUTOMATION CONFERENCE, DAC , 2023 . |
| MLA | Liu, Qinghai et al. "Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints" . | IEEE DESIGN AUTOMATION CONFERENCE, DAC (2023) . |
| APA | Liu, Qinghai , Tang, Qinfei , Chen, Jiarui , Chen, Chuandong , Zhu, Ziran , He, Huan et al. Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints . | IEEE DESIGN AUTOMATION CONFERENCE, DAC , 2023 . |
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在我国电力系统中，配电站属于电力网络边缘节点，是电力系统中的重要环节。然而，人工巡检或一些传统硬件设备的数据采集手段，由于成本及效率等问题，已经无法匹配当下的安防巡检需求。针对此问题，本文提出一种基于现场可编程门阵列（FPGA）的智能配电站安防巡检解决方案。首先利用YOLOv4-tiny网络实现安全帽佩戴检测、工作服着装检测、越界预警识别等功能，其准确率可达93.5%；其次针对配电站的应用场景，本文利用FPGA在边缘设备上实现实时检测的效果，并从并行展开及流水线等方面进行加速优化。实验结果表明，该系统可在ZCU102平台上实现每秒传输帧数为68的检测速度，整体平均性能达到228十亿次运算/秒。
Keyword ：
YOLO YOLO 安防巡检 安防巡检 智能配电站 智能配电站 现场可编程门阵列(FPGA) 现场可编程门阵列(FPGA)
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| GB/T 7714 | 陈标发 , 陈传东 , 魏榕山 et al. 基于现场可编程门阵列的智能配电站安防巡检系统设计与实现 [J]. | 电气技术 , 2022 , 23 (05) : 34-38 . |
| MLA | 陈标发 et al. "基于现场可编程门阵列的智能配电站安防巡检系统设计与实现" . | 电气技术 23 . 05 (2022) : 34-38 . |
| APA | 陈标发 , 陈传东 , 魏榕山 , 罗海波 . 基于现场可编程门阵列的智能配电站安防巡检系统设计与实现 . | 电气技术 , 2022 , 23 (05) , 34-38 . |
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逃逸布线是印刷电路板设计的一个重要组成部分.针对并行逃逸布线的方法用于较大规模电路板布线时速度慢且结果不够好的问题,该文提出一种结合改进A*算法与拆线重布的有序逃逸布线方法.首先,通过代价预估函数确定引脚的布线顺序,使用改进A*算法初始化有序逃逸布线.接着,优化同长度布线路径,调整拥挤区域布线路径.最后,使用A*算法和广度优先搜索进行拆线重布.实验结果表明,该方法对给出的所有测试用例都实现了100％的逃逸,得到有序逃逸路径的可行解非常接近最优解,CPU时间比布尔可满足性问题(SAT)算法与最小费用多商品流(MMCF)算法平均减少分别约为95.6％,?97.8％,总体线长也接近最优.提出的方法能够明显减少寻找可行解的时间,提高布线质量.
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| GB/T 7714 | 邓新国 , 叶似锦 , 陈家瑞 et al. 结合改进A*算法与拆线重布的有序逃逸布线 [J]. | 电子与信息学报 , 2021 , 43 (6) : 1609-1616 . |
| MLA | 邓新国 et al. "结合改进A*算法与拆线重布的有序逃逸布线" . | 电子与信息学报 43 . 6 (2021) : 1609-1616 . |
| APA | 邓新国 , 叶似锦 , 陈家瑞 , 陈传东 . 结合改进A*算法与拆线重布的有序逃逸布线 . | 电子与信息学报 , 2021 , 43 (6) , 1609-1616 . |
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逃逸布线是印刷电路板设计的一个重要组成部分。针对并行逃逸布线的方法用于较大规模电路板布线时速度慢且结果不够好的问题,该文提出一种结合改进A~*算法与拆线重布的有序逃逸布线方法。首先,通过代价预估函数确定引脚的布线顺序,使用改进A~*算法初始化有序逃逸布线。接着,优化同长度布线路径,调整拥挤区域布线路径。最后,使用A~*算法和广度优先搜索进行拆线重布。实验结果表明,该方法对给出的所有测试用例都实现了100%的逃逸,得到有序逃逸路径的可行解非常接近最优解,CPU时间比布尔可满足性问题(SAT)算法与最小费用多商品流(MMCF)算法平均减少分别约为95.6%, 97.8%,总体线长也接近最优。提出的...
Keyword ：
A~*算法 A~*算法 拆线重布 拆线重布 最短路径 最短路径 有序逃逸布线 有序逃逸布线
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| GB/T 7714 | 邓新国 , 叶似锦 , 陈家瑞 et al. 结合改进A~*算法与拆线重布的有序逃逸布线 [J]. | 电子与信息学报 , 2021 , 43 (06) : 1609-1616 . |
| MLA | 邓新国 et al. "结合改进A~*算法与拆线重布的有序逃逸布线" . | 电子与信息学报 43 . 06 (2021) : 1609-1616 . |
| APA | 邓新国 , 叶似锦 , 陈家瑞 , 陈传东 . 结合改进A~*算法与拆线重布的有序逃逸布线 . | 电子与信息学报 , 2021 , 43 (06) , 1609-1616 . |
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Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.
Keyword ：
address mapping address mapping DRAM DRAM memory access optimization memory access optimization memory controller memory controller
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| GB/T 7714 | Wei, Rongshan , Li, Chenjia , Chen, Chuandong et al. Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller [J]. | ELECTRONICS , 2021 , 10 (4) . |
| MLA | Wei, Rongshan et al. "Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller" . | ELECTRONICS 10 . 4 (2021) . |
| APA | Wei, Rongshan , Li, Chenjia , Chen, Chuandong , Sun, Guangyu , He, Minghua . Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller . | ELECTRONICS , 2021 , 10 (4) . |
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