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< Page ,Total 1 >
Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range SCIE
期刊论文 | 2025 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
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Abstract :

This paper describes the analysis and design of a discrete-time (DT) fully dynamic 3-0 multi-stage noise-shaping (MASH) delta-sigma (Delta Sigma) analog-to-digital converter (ADC). Through system-level analysis, error source analysis, nonlinearity analysis and modeling of the integrators, and detailed considerations for circuit implementation, the trade-offs between design parameters in the 3-0 MASH Delta Sigma ADC were evaluated. The proposed ADC is fabricated and measured in a 180 nm CMOS process, achieving a DR, peak SNDR, and SFDR of 100.2 dB, 98.5 dB, and 116.7 dB, respectively, within a 2.56 kHz bandwidth, consuming only 20.1 mu W. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR are 179.6 dB and 181.3 dB, respectively. The measurement results of the prototype 3-0 MASH Delta Sigma ADC closely matched the theoretical predictions. This consistency between the measurements and the theoretical analysis confirms the reliability of the design approach in achieving the expected performance.

Keyword :

Active filters Active filters analog-to-digital converter (ADC) analog-to-digital converter (ADC) Circuits Circuits delta-sigma (Delta Sigma) delta-sigma (Delta Sigma) Digital filters Digital filters discrete-time (DT) discrete-time (DT) Energy efficiency Energy efficiency Gain Gain Multi-stage noise shaping Multi-stage noise shaping Multi-stage noise-shaping (MASH) Multi-stage noise-shaping (MASH) Noise Noise Power demand Power demand Quantization (signal) Quantization (signal) Transfer functions Transfer functions

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GB/T 7714 Wei, Cong , Huang, Lijie , Wei, Rongshan et al. Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 .
MLA Wei, Cong et al. "Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2025) .
APA Wei, Cong , Huang, Lijie , Wei, Rongshan , Lu, Xiaoqiang , Tan, Zhichao . Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 .
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