Query：
学者姓名：林智锋
Refining：
Year
Type
Indexed by
Source
Complex
Co-
Language
Clean All
Abstract ：
Recently, hybrid-row-height designs have been introduced to achieve performance and area co-optimization in advanced nodes. Hybrid-row-height designs incur challenging issues to layout due to the heterogeneous cell and row structures. In this paper, we present an effective algorithm to address the hybrid-row-height placement problem in two major stages: (1) global placement, and (2) legalization. Inspired by the multi-channel processing method in convolutional neural networks (CNN), we use the feature extraction technique to equivalently transform the hybrid-row-height global placement problem into two sub-problems that can be solved effectively. We propose a multi-layer nonlinear framework with alignment guidance and a self-adaptive parameter adjustment scheme, which can obtain a high-quality solution to the hybrid-row-height global placement problem. In the legalization stage, we formulate the hybrid-row-height legalization problem into a convex quadratic programming (QP) problem, then apply the robust modulus-based matrix splitting iteration method (RMMSIM) to solve the QP efficiently. After RMMSIM-based global legalization, Tetris-like allocation is used to resolve remaining physical violations. Compared with the state-of-the-art work, experiments on the 2015 ISPD Contest benchmarks show that our algorithm can achieve 7% shorter final total wirelength and 2.23x speedup.
Keyword ：
Hybrid-row-height structure Hybrid-row-height structure Nonlinear placement Nonlinear placement Physical design Physical design Placement Placement
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Wen, Yuan , Zhu, Benchao , Lin, Zhifeng et al. Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 300-305 . |
| MLA | Wen, Yuan et al. "Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 300-305 . |
| APA | Wen, Yuan , Zhu, Benchao , Lin, Zhifeng , Chen, Jianli . Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 300-305 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer.
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Wei, Min , Tong, Xingyu , Cai, Zhijie et al. An Analytical Placement Algorithm with Routing topology Optimization [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 294-299 . |
| MLA | Wei, Min et al. "An Analytical Placement Algorithm with Routing topology Optimization" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 294-299 . |
| APA | Wei, Min , Tong, Xingyu , Cai, Zhijie , Zou, Peng , Lin, Zhifeng , Chen, Jianli . An Analytical Placement Algorithm with Routing topology Optimization . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 294-299 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
The expansion of the IC dimension is ushering in a morethan-Moore era, necessitating corresponding EDA tools. Existing TSVbased 3D placers focus on minimizing cuts, while burgeoning F2F-bonded ICs features dense interconnection between two planar die. Towards this novel structure, we proposed an integrated adaptation methodology upon mature one-die-based placement strategies. First, we instructively utilized a one-die placer to provide a statistical looking-ahead net diagnosis. The netlist henceforth shall be coarsened topologically and geometrically with a multi-level framework. Level by level, the partition will be refined according to a multi-objective gain formulation, including cut expectation, heterogeneous row height, and balanced cell distribution. Given the partition, we synchronized the behavior of analytical planar placers by balancing the density and wirelength objective function among asymmetric layers. Finally, the result will be further improved by heuristic bonding terminals' detail placement and a post-place partition adjustment. Compared to the top three winners of the 2022 CAD Contest at ICCAD, experiment results show that our fine-grained fusion upon partitioning and placement gets the best normalized average wirelength with a fairly reasonable runtime under all 3D architectural constraints.
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Tong, Xingyu , Cai, Zhijie , Zou, Peng et al. O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 71-76 . |
| MLA | Tong, Xingyu et al. "O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 71-76 . |
| APA | Tong, Xingyu , Cai, Zhijie , Zou, Peng , Wei, Min , Wen, Yuan , Lin, Zhifeng et al. O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 71-76 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Placement is a critical stage for VLSI timing closure. A global placer without considering timing delay might lead to inferior solutions with timing violations. This paper proposes an electrostatics-based timing optimization method for VLSI global placement. Simulating the optimal buffering behavior, we first present an analytical delay model to calculate each connection delay accurately. Then, a timing-driven block distribution scheme is developed to optimize the critical path delay while considering the path-sharing effect. Finally, we develop a timing-aware precondition technique to speed up placement convergence without degrading timing quality. Experimental results on industrial benchmark suites show that our timing-driven placement algorithm outperforms a leading commercial tool by 6.7% worst negative slack (WNS) and 21.6% total negative slack (TNS). © 2024 EDAA.
Keyword ：
Dissociation Dissociation Electrostatics Electrostatics Timing circuits Timing circuits VLSI circuits VLSI circuits
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Lin, Zhifeng , Wei, Min , Chen, Yilu et al. Electrostatics-Based Analytical Global Placement for Timing Optimization [C] . 2024 . |
| MLA | Lin, Zhifeng et al. "Electrostatics-Based Analytical Global Placement for Timing Optimization" . (2024) . |
| APA | Lin, Zhifeng , Wei, Min , Chen, Yilu , Zou, Peng , Chen, Jianli , Chang, Yao-Wen . Electrostatics-Based Analytical Global Placement for Timing Optimization . (2024) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
In global routing, congestion and running time are the key factors that affect the quality of the solution. With the rapid growth of integrated chip scale, striking a balance between running time and congestion has become a bottleneck in improving design quality. In this paper, we propose a highly efficient and effective global router to address this challenge. We first propose an efficient R-tree-based compatible routing region partitioning algorithm for collecting routable regions, which offers robust support for ideal parallel routing scheduling. Then, taking into account the effect of the barrel effect on congestion evaluation and the detrimental impact of loops, a congestion-driven initial parallel routing scheme is proposed to enhance routability in the triaxial pattern routing structure. After that, we develop an accurate congestion estimation model and an optimized path-searching scheme, which are instrumental in effectively managing smaller congestion gradient variations and guiding efficient congestion reduction. We evaluate the performance of our algorithm on the ISPD 2018 and ISPD 2019 contest benchmark suites and compare it with the state-of-the-art work. Experimental results show that our proposed algorithm significantly reduces 71% overflows, improving 65% running time, and the total wirelength is even smaller. © 2024 Elsevier B.V.
Keyword ：
Congestion Congestion Global routing Global routing Parallel routing Parallel routing Physical design Physical design Wirelength Wirelength
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Bai, X. , Chen, Y. , Lin, Z. et al. A fast and high-performance global router with enhanced congestion control [J]. | Integration , 2024 , 99 . |
| MLA | Bai, X. et al. "A fast and high-performance global router with enhanced congestion control" . | Integration 99 (2024) . |
| APA | Bai, X. , Chen, Y. , Lin, Z. , Wei, M. , Cai, Z. , Zhu, Z. et al. A fast and high-performance global router with enhanced congestion control . | Integration , 2024 , 99 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Placement is a critical stage for VLSI timing closure. A global placer without considering timing delay might lead to inferior solutions with timing violations. This paper proposes an electrostatics-based timing optimization method for VLSI global placement. Simulating the optimal buffering behavior, we first present an analytical delay model to calculate each connection delay accurately. Then, a timing-driven block distribution scheme is developed to optimize the critical path delay while considering the path-sharing effect. Finally, we develop a timing-aware precondition technique to speed up placement convergence without degrading timing quality. Experimental results on industrial benchmark suites show that our timing-driven placement algorithm outperforms a leading commercial tool by 6.7% worst negative slack (WNS) and 21.6% total negative slack (TNS). © 2024 EDAA.
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Lin, Z. , Wei, M. , Chen, Y. et al. Electrostatics-Based Analytical Global Placement for Timing Optimization [未知]. |
| MLA | Lin, Z. et al. "Electrostatics-Based Analytical Global Placement for Timing Optimization" [未知]. |
| APA | Lin, Z. , Wei, M. , Chen, Y. , Zou, P. , Chen, J. , Chang, Y.-W. . Electrostatics-Based Analytical Global Placement for Timing Optimization [未知]. |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Routability estimation identifies potentially congested areas in advance to achieve high-quality routing solutions. To improve the routing quality, this paper presents a deep learning-based congestion estimation algorithm, which serves to guide the initial pattern routing of a global router to reduce unexpected overflows. Unlike existing methods based on traditional compressed 2D features for model training and prediction, our algorithm extracts appropriate 3D features from the placed netlists. Furthermore, an improved RUDY (Rectangular Uniform wire DensitY) method is developed to estimate 3D routing demands. For the model selection, we employ the U-net model with good image prediction ability as a routability estimator, and the prediction results are used for guiding the initial routing process. Since our training set is formed by cropping training designs, the structural information between two adjacent cropped designs may be missed. Hence, we divide experiments into two parts, experiments based on normal designs and experiments based on big designs. Compared with the state-of-the-art method, experimental results show that our routability estimator can significantly improve the Pearson Correlation Coefficient (PCC) index and reduce the Mean Absolute Normalized Error (MANE) and the Standard Deviation in the Normalized Error (SDNE). Furthermore, our congestion-guided global routing can reduce the routing overflows, wirelength, and via count both on normal designs and big designs, compared to CUGR.
Keyword ：
Deep learning Deep learning Machine learning Machine learning Physical design Physical design Routing congestion Routing congestion Very large-scale integration Very large-scale integration
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Chen, Yilu , Su, Miaodi , Ding, Hongzhi et al. High-correlation 3D routability estimation for congestion-guided global routing [J]. | JOURNAL OF SUPERCOMPUTING , 2023 , 80 (3) : 3114-3141 . |
| MLA | Chen, Yilu et al. "High-correlation 3D routability estimation for congestion-guided global routing" . | JOURNAL OF SUPERCOMPUTING 80 . 3 (2023) : 3114-3141 . |
| APA | Chen, Yilu , Su, Miaodi , Ding, Hongzhi , Weng, Shaohong , Lin, Zhifeng , Bai, Xiqiong . High-correlation 3D routability estimation for congestion-guided global routing . | JOURNAL OF SUPERCOMPUTING , 2023 , 80 (3) , 3114-3141 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Modern circuits often contain standard cells of different threshold voltages (multi-VTs) to achieve a better trade-off between timing and power consumption. Due to the heterogeneous cell structures, the multiVTs cells impose various implant layer constraints, further complicating the already time-consuming filler cell insertion process. In this paper, we present a fast and near-optimal algorithm to solve the filler insertion problem with complex implant layer rules and minimum filler width constraints. We first propose an inference-driven detecting algorithm to identify each design rule violation accurately. Then, a dynamic-programming-based insertion method is developed to reduce the implant layer violations. Finally, we design a contour-driven violation refinement strategy to further improve manufacturability. Experimental results show that our algorithm can reduce the number of violations significantly compared with state-of-the-art works. Besides, with our identifier in the legalization stage, we can avoid conflicts in advance and solve almost all violations after filler insertion in industrial cases.
Keyword ：
dynamic programming dynamic programming filler insertion filler insertion implant layer constraints implant layer constraints rule generation rule generation
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Zou, Peng , Chen, Guohao , Lin, Zhifeng et al. Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints [J]. | IEEE DESIGN AUTOMATION CONFERENCE, DAC , 2023 . |
| MLA | Zou, Peng et al. "Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints" . | IEEE DESIGN AUTOMATION CONFERENCE, DAC (2023) . |
| APA | Zou, Peng , Chen, Guohao , Lin, Zhifeng , Yu, Jun , Chen, Jianli . Toward Optimal Filler Cell Insertion with Complex Implant Layer Constraints . | IEEE DESIGN AUTOMATION CONFERENCE, DAC , 2023 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
The complexity of physical verification increases rapidly with fast shrinking technology nodes. Considering only design rule checking (DRC) constraints or lithography models cannot capture the side physical effects in the fabrication process well. Thus, it is desirable to consider a more general physical verification problem with various types of hotspots. In this paper, we apply machine learning which is based on pixel-based feature extraction to deal with the generalized hotspot detection problem. First, a two-dimensional discrete Fourier transformation-based pixel extraction method is proposed to alleviate the shifting effect and produce stable hotspot features. Then, a pattern-based layout scanning approach is developed to enhance the program efficiency while preserving good detection accuracy. Finally, we design two false alarm reduction strategies to effectively reduce the number of detected nonhotspots and further improve the accuracy of hotspot position. Experimental results based on the industrial benchmarks show that our algorithm outperforms three competitive works in terms of accuracy, false alarm rate, efficiency, and time.
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Lin, Zhifeng , Gu, Zhenghua , Huang, Zhipeng et al. Hotspot Detection with Machine Learning Based on Pixel-Based Feature Extraction [J]. | SCIENTIFIC PROGRAMMING , 2022 , 2022 . |
| MLA | Lin, Zhifeng et al. "Hotspot Detection with Machine Learning Based on Pixel-Based Feature Extraction" . | SCIENTIFIC PROGRAMMING 2022 (2022) . |
| APA | Lin, Zhifeng , Gu, Zhenghua , Huang, Zhipeng , Bai, Xiqiong , Luo, Lixuan , Lin, Geng . Hotspot Detection with Machine Learning Based on Pixel-Based Feature Extraction . | SCIENTIFIC PROGRAMMING , 2022 , 2022 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
As interconnects dominate circuit performance in modern field programmable gate arrays (FPGAs), placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints and, thus, may lead to illegal routing solutions. In this article, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves a 5.1% improvement in worst slack and produce placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado.
Keyword ：
Computer architecture Computer architecture Delays Delays Field programmable gate array (FPGA) Field programmable gate array (FPGA) Field programmable gate arrays Field programmable gate arrays Law Law physical design physical design placement placement Random access memory Random access memory Routing Routing Table lookup Table lookup timing timing
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Lin, Zhifeng , Xie, Yanyue , Zou, Peng et al. An Incremental Placement Flow for Advanced FPGAs With Timing Awareness [J]. | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2022 , 41 (9) : 3092-3103 . |
| MLA | Lin, Zhifeng et al. "An Incremental Placement Flow for Advanced FPGAs With Timing Awareness" . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 41 . 9 (2022) : 3092-3103 . |
| APA | Lin, Zhifeng , Xie, Yanyue , Zou, Peng , Wang, Sifei , Yu, Jun , Chen, Jianli . An Incremental Placement Flow for Advanced FPGAs With Timing Awareness . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2022 , 41 (9) , 3092-3103 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Export
| Results： |
Selected to |
| Format： |
