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学者姓名：林智锋
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The Ordered Escape Routing (OER) problem, which is an NP-hard problem, is critical to PCB design. Primary methods based on integer linear programming (ILP) work well on small-scale PCBs with fewer pins. However, when dealing with large-scale instances, traditional ILP strategies frequently cause time violations as the number of variables increases due to time-consuming preprocessing. In addition, heuristic algorithms have a time advantage when dealing with specific problems. In this paper, We propose an efficient two-stage escape routing method that employs LP for global routing and uses a heuristic algorithm to deal with the path intersection problem to minimize wiring length and runtime for large-scale PCBs. We first model the OER problem as a min-cost multi-commodity flow problem and use ILP to solve it. Then, we relax the non-crossing constraints and transform the ILP model into an LP model to reduce the runtime. we also construct a crossing graph according to the intersection of routing paths and propose a heuristic algorithm to locate congestion quickly. Finally, we reduce the local area capacity and allow global automatic congestion optimization. Compared with the state-of-the-art work, experimental results show that our method can reduce the routing time by 60% and handle larger-scale PCB escape routing problems.
Keyword ：
Heuristic algorithm Heuristic algorithm Linear programming Linear programming Min-cost multi-commodity flow Min-cost multi-commodity flow Ordered escape routing Ordered escape routing
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| GB/T 7714 | Lin, Disi , Chen, Chuandong , Wei, Rongshan et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB [J]. | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
| MLA | Lin, Disi et al. "Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB" . | INTEGRATION-THE VLSI JOURNAL 100 (2025) . |
| APA | Lin, Disi , Chen, Chuandong , Wei, Rongshan , Liu, Qinghai , He, Huan , Zhu, Ziran et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB . | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
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As the feature sizes keep shrinking, interconnect delays have become a major limiting factor for FPGA timing closure. Traditional placement algorithms that address wirelength alone are no longer sufficient to close timing, especially for the large-scale heterogeneous FPGAs. In this paper, we propose an analytical placement algorithm for FPGA timing optimization. By leveraging the look-up table technique, we first present a smoothed routing-architecture-aware timing model to calculate each connection delay rapidly. Then, an effective wirelength and timing co-optimization strategy is developed to produce high-quality placements without timing violations. Finally, a delay optimal region-based detail placement strategy is designed to further improve the timing performance. Compared with Vivado 2023.1 on AMD benchmark suites for xc7k325t device, experimental results show that our algorithm achieves not only a 3.2% improvement in worst slack, but also a 2.5% reduction for routed wirelength.
Keyword ：
Field programmable gate arrays Field programmable gate arrays Physical design Physical design Placement Placement Timing optimization Timing optimization
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| GB/T 7714 | Lin, Zhifeng , Chen, Yilu , Xie, Yanyue et al. An analytical timing-driven placer for modern heterogeneous FPGAs [J]. | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (1) . |
| MLA | Lin, Zhifeng et al. "An analytical timing-driven placer for modern heterogeneous FPGAs" . | JOURNAL OF SUPERCOMPUTING 81 . 1 (2025) . |
| APA | Lin, Zhifeng , Chen, Yilu , Xie, Yanyue , Chen, Chuandong , Yu, Jun , Chen, Jianli . An analytical timing-driven placer for modern heterogeneous FPGAs . | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (1) . |
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A growing recognition of potential vulnerabilities to layout-level Hardware Trojan (HT) attacks has spurred significant research efforts aimed at enhancing the resilience of ICs against such threats. However, traditional hardware security has been predominantly concerned with defensive measures, often overlooking the original key metrics in physical design evaluation: power, performance, and area (PPA). This study introduces an automated methodology incorporating HT considerations into the practical physical design process. Utilizing a Bayesian optimization framework, it effectively navigates the operation of commercial physical implementation tools in the solution space of hyper-parameter settings. Innovative strategies inspired by mosaic techniques, such as cell shifting and buffer insertion, realize additional improvements in layout-level trojan prevention. Comparative evaluations have shown that our approach outperforms leading entries from the ISPD 2023 Contest in terms of PPA and HT prevention metrics, thereby providing significant insights into the synergy between these critical factors. © 2024 Copyright is held by the owner/author(s).
Keyword ：
Computer viruses Computer viruses Computer worms Computer worms
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| GB/T 7714 | Tong, Xingyu , Chen, Guohao , Wei, Min et al. Layout-level Hardware Trojan Prevention in the Context of Physical Design [C] . 2025 . |
| MLA | Tong, Xingyu et al. "Layout-level Hardware Trojan Prevention in the Context of Physical Design" . (2025) . |
| APA | Tong, Xingyu , Chen, Guohao , Wei, Min , Cai, Zhijie , Zou, Peng , Lin, Zhifeng et al. Layout-level Hardware Trojan Prevention in the Context of Physical Design . (2025) . |
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Recently, hybrid-row-height designs have been introduced to achieve performance and area co-optimization in advanced nodes. Hybrid-row-height designs incur challenging issues to layout due to the heterogeneous cell and row structures. In this paper, we present an effective algorithm to address the hybrid-row-height placement problem in two major stages: (1) global placement, and (2) legalization. Inspired by the multi-channel processing method in convolutional neural networks (CNN), we use the feature extraction technique to equivalently transform the hybrid-row-height global placement problem into two sub-problems that can be solved effectively. We propose a multi-layer nonlinear framework with alignment guidance and a self-adaptive parameter adjustment scheme, which can obtain a high-quality solution to the hybrid-row-height global placement problem. In the legalization stage, we formulate the hybrid-row-height legalization problem into a convex quadratic programming (QP) problem, then apply the robust modulus-based matrix splitting iteration method (RMMSIM) to solve the QP efficiently. After RMMSIM-based global legalization, Tetris-like allocation is used to resolve remaining physical violations. Compared with the state-of-the-art work, experiments on the 2015 ISPD Contest benchmarks show that our algorithm can achieve 7% shorter final total wirelength and 2.23x speedup.
Keyword ：
Hybrid-row-height structure Hybrid-row-height structure Nonlinear placement Nonlinear placement Physical design Physical design Placement Placement
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| GB/T 7714 | Wen, Yuan , Zhu, Benchao , Lin, Zhifeng et al. Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 300-305 . |
| MLA | Wen, Yuan et al. "Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 300-305 . |
| APA | Wen, Yuan , Zhu, Benchao , Lin, Zhifeng , Chen, Jianli . Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 300-305 . |
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The expansion of the IC dimension is ushering in a morethan-Moore era, necessitating corresponding EDA tools. Existing TSVbased 3D placers focus on minimizing cuts, while burgeoning F2F-bonded ICs features dense interconnection between two planar die. Towards this novel structure, we proposed an integrated adaptation methodology upon mature one-die-based placement strategies. First, we instructively utilized a one-die placer to provide a statistical looking-ahead net diagnosis. The netlist henceforth shall be coarsened topologically and geometrically with a multi-level framework. Level by level, the partition will be refined according to a multi-objective gain formulation, including cut expectation, heterogeneous row height, and balanced cell distribution. Given the partition, we synchronized the behavior of analytical planar placers by balancing the density and wirelength objective function among asymmetric layers. Finally, the result will be further improved by heuristic bonding terminals' detail placement and a post-place partition adjustment. Compared to the top three winners of the 2022 CAD Contest at ICCAD, experiment results show that our fine-grained fusion upon partitioning and placement gets the best normalized average wirelength with a fairly reasonable runtime under all 3D architectural constraints.
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| GB/T 7714 | Tong, Xingyu , Cai, Zhijie , Zou, Peng et al. O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 71-76 . |
| MLA | Tong, Xingyu et al. "O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 71-76 . |
| APA | Tong, Xingyu , Cai, Zhijie , Zou, Peng , Wei, Min , Wen, Yuan , Lin, Zhifeng et al. O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 71-76 . |
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Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer.
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| GB/T 7714 | Wei, Min , Tong, Xingyu , Cai, Zhijie et al. An Analytical Placement Algorithm with Routing topology Optimization [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 294-299 . |
| MLA | Wei, Min et al. "An Analytical Placement Algorithm with Routing topology Optimization" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 294-299 . |
| APA | Wei, Min , Tong, Xingyu , Cai, Zhijie , Zou, Peng , Lin, Zhifeng , Chen, Jianli . An Analytical Placement Algorithm with Routing topology Optimization . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 294-299 . |
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Placement is a critical stage for VLSI timing closure. A global placer without considering timing delay might lead to inferior solutions with timing violations. This paper proposes an electrostatics-based timing optimization method for VLSI global placement. Simulating the optimal buffering behavior, we first present an analytical delay model to calculate each connection delay accurately. Then, a timing-driven block distribution scheme is developed to optimize the critical path delay while considering the path-sharing effect. Finally, we develop a timing-aware precondition technique to speed up placement convergence without degrading timing quality. Experimental results on industrial benchmark suites show that our timing-driven placement algorithm outperforms a leading commercial tool by 6.7% worst negative slack (WNS) and 21.6% total negative slack (TNS).
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| GB/T 7714 | Lin, Zhifeng , Wei, Min , Chen, Yilu et al. Electrostatics-Based Analytical Global Placement for Timing Optimization [J]. | 2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE , 2024 . |
| MLA | Lin, Zhifeng et al. "Electrostatics-Based Analytical Global Placement for Timing Optimization" . | 2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE (2024) . |
| APA | Lin, Zhifeng , Wei, Min , Chen, Yilu , Zou, Peng , Chen, Jianli , Chang, Yao-Wen . Electrostatics-Based Analytical Global Placement for Timing Optimization . | 2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE , 2024 . |
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Abstract ：
Placement is a critical stage for VLSI timing closure. A global placer without considering timing delay might lead to inferior solutions with timing violations. This paper proposes an electrostatics-based timing optimization method for VLSI global placement. Simulating the optimal buffering behavior, we first present an analytical delay model to calculate each connection delay accurately. Then, a timing-driven block distribution scheme is developed to optimize the critical path delay while considering the path-sharing effect. Finally, we develop a timing-aware precondition technique to speed up placement convergence without degrading timing quality. Experimental results on industrial benchmark suites show that our timing-driven placement algorithm outperforms a leading commercial tool by 6.7% worst negative slack (WNS) and 21.6% total negative slack (TNS). © 2024 EDAA.
Keyword ：
Dissociation Dissociation Electrostatics Electrostatics Timing circuits Timing circuits VLSI circuits VLSI circuits
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| GB/T 7714 | Lin, Zhifeng , Wei, Min , Chen, Yilu et al. Electrostatics-Based Analytical Global Placement for Timing Optimization [C] . 2024 . |
| MLA | Lin, Zhifeng et al. "Electrostatics-Based Analytical Global Placement for Timing Optimization" . (2024) . |
| APA | Lin, Zhifeng , Wei, Min , Chen, Yilu , Zou, Peng , Chen, Jianli , Chang, Yao-Wen . Electrostatics-Based Analytical Global Placement for Timing Optimization . (2024) . |
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Abstract ：
Placement is a critical stage for VLSI timing closure. A global placer without considering timing delay might lead to inferior solutions with timing violations. This paper proposes an electrostatics-based timing optimization method for VLSI global placement. Simulating the optimal buffering behavior, we first present an analytical delay model to calculate each connection delay accurately. Then, a timing-driven block distribution scheme is developed to optimize the critical path delay while considering the path-sharing effect. Finally, we develop a timing-aware precondition technique to speed up placement convergence without degrading timing quality. Experimental results on industrial benchmark suites show that our timing-driven placement algorithm outperforms a leading commercial tool by 6.7% worst negative slack (WNS) and 21.6% total negative slack (TNS). © 2024 EDAA.
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| GB/T 7714 | Lin, Z. , Wei, M. , Chen, Y. et al. Electrostatics-Based Analytical Global Placement for Timing Optimization [未知]. |
| MLA | Lin, Z. et al. "Electrostatics-Based Analytical Global Placement for Timing Optimization" [未知]. |
| APA | Lin, Z. , Wei, M. , Chen, Y. , Zou, P. , Chen, J. , Chang, Y.-W. . Electrostatics-Based Analytical Global Placement for Timing Optimization [未知]. |
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Placement is a critical step in the modern VLSI design flow, as it dramatically determines the performance of circuit designs. Most placement algorithms estimate the design performance with a half-perimeter wirelength (HPWL) and target it as their optimization objective. The wirelength model used by these algorithms limits their ability to optimize the internal routing topology, which can lead to discrepancies between estimates and the actual routing wirelength. This paper proposes an analytical placement algorithm to optimize the internal routing topology. We first introduce a differential wirelength model in the global placement stage based on an ideal routing topology RSMT. Through screening and tracing various segments, this model can generate meaningful gradients for interior points during gradient computation. Then, after global placement, we propose a cell refinement algorithm and further optimize the routing wirelength with swift density control. Experiments on ICCAD2015 benchmarks show that our algorithm can achieve a 3% improvement in routing wirelength, 0.8% in HPWL, and 23.8% in TNS compared with the state-of-the-art analytical placer. On industrial benchmarks, our algorithm can also achieve a 10.6% improvement in routing wirelength, 27.3% in WNS, and 34.4% in TNS.
Keyword ：
Analytical placement Analytical placement Physical design Physical design Refinement placement Refinement placement Wirelength model Wirelength model
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| GB/T 7714 | Wei, Min , Tong, Xingyu , Cai, Zhijie et al. An analytical placement algorithm with looking-ahead routing topology optimization [J]. | INTEGRATION-THE VLSI JOURNAL , 2024 , 100 . |
| MLA | Wei, Min et al. "An analytical placement algorithm with looking-ahead routing topology optimization" . | INTEGRATION-THE VLSI JOURNAL 100 (2024) . |
| APA | Wei, Min , Tong, Xingyu , Cai, Zhijie , Zou, Peng , Lin, Zhifeng , Chen, Jianli . An analytical placement algorithm with looking-ahead routing topology optimization . | INTEGRATION-THE VLSI JOURNAL , 2024 , 100 . |
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