Routing　is　a　critical　and　time-consuming　stage　in　circuit　physical　design.　The　typical　approach　involves　2D　routing　followed　by　3D　layer　assignment,　with　most　state-of-the-art　methods　using　sequential　assignments,　which　limits　the　solution　space　due　to　the　fixed　order　in　which　nets　are　processed.　This　paper　proposes　a　two-stage　layer　assignment　paradigm　inspired　by　the　placement　process.　First,　we　apply　an　analytical　method　to　simultaneously　assign　layers　for　all　nets,　leveraging　GPU　acceleration　to　enhance　computational　efficiency.　Then,　a　simulated　annealing　algorithm　further　optimizes　the　segment　assignments.　Experimental　results　show　that,　compared　to　state-of-the-art　sequential　and　concurrent　layer　assignment　algorithms,　our　method　reduces　via　count　by　16.9%　and　1.5%　in　global　routing　and　by　5.3%　and　3.5%　in　detailed　routing,　respectively,　with　minimal　wirelength　increases.　Additionally,　our　algorithm　achieves　the　fewest　DRC　violations　across　all　benchmarks.　©　2025　IEEE.