As　a　new　generation　of　flow-based　microfluidics,　fully　programmable　valve　array　(FPVA)　biochips　have　gained　widespread　adoption　as　a　biochemical　experimental　platform,　thanks　to　their　enhanced　programmability　and　flexibility.　Environmental　and　human　factors,　however,　often　introduce　physical　faults　during　the　manufacturing　process,　such　as　channel　blockage　and　leakage,　which,　undoubtedly,　can　affect　the　results　of　bioassays　and　even　cause　execution　failure.　In　this　article,　we　focus　on　the　fault-tolerant　co-design　of　flow　and　control　layers　in　FPVA　biochips　for　the　first　time.　For　the　flow　layer,　three　dynamic　fault-tolerant　techniques,　i.e.,　a　cell　function　conversion　method,　a　bidirectional　redundancy　scheme,　and　a　fault　mapping　method,　are　presented　and　integrated　into　the　device　placement　and　flow　routing　stages.　As　a　consequence,　we　further　realize　an　efficient　and　effective　fault-tolerance-oriented　physical　design　method,　thus　ensuring　the　robustness　of　chip　architecture　and　correctness　of　assay　outcomes.　For　the　control　layer,　we　design　another　three　fault-tolerant　techniques,　including　a　series　duplication　scheme　of　leakage　valves,　allocation　and　merging　rules　of　backup　valves,　and　a　logic　conflict-aware　adjustment　strategy　of　redundant　architecture.　Based　on　these　techniques,　we　construct　a　fault-tolerant　control　system　to　realize　dynamic　recovery　of　control　signals.　Experimental　results　on　multiple　test　cases　demonstrate　that　the　proposed　method　can　produce　optimized　fault-tolerant　FPVA　architectures　with　low-fabrication　cost,　high-execution　efficiency,　and　high-fault-tolerance　success　rate.　©　1982-2012　IEEE.