A　growing　recognition　of　potential　vulnerabilities　to　layout-level　Hardware　Trojan　(HT)　attacks　has　spurred　significant　research　efforts　aimed　at　enhancing　the　resilience　of　ICs　against　such　threats.　However,　traditional　hardware　security　has　been　predominantly　concerned　with　defensive　measures,　often　overlooking　the　original　key　metrics　in　physical　design　evaluation:　power,　performance,　and　area　(PPA).　This　study　introduces　an　automated　methodology　incorporating　HT　considerations　into　the　practical　physical　design　process.　Utilizing　a　Bayesian　optimization　framework,　it　effectively　navigates　the　operation　of　commercial　physical　implementation　tools　in　the　solution　space　of　hyper-parameter　settings.　Innovative　strategies　inspired　by　mosaic　techniques,　such　as　cell　shifting　and　buffer　insertion,　realize　additional　improvements　in　layout-level　trojan　prevention.　Comparative　evaluations　have　shown　that　our　approach　outperforms　leading　entries　from　the　ISPD　2023　Contest　in　terms　of　PPA　and　HT　prevention　metrics,　thereby　providing　significant　insights　into　the　synergy　between　these　critical　factors.　©　2024　Copyright　is　held　by　the　owner/author(s).