In　global　routing,　congestion　and　running　time　are　the　key　factors　that　affect　the　quality　of　the　solution.　With　the　rapid　growth　of　integrated　chip　scale,　striking　a　balance　between　running　time　and　congestion　has　become　a　bottleneck　in　improving　design　quality.　In　this　paper,　we　propose　a　highly　efficient　and　effective　global　router　to　address　this　challenge.　We　first　propose　an　efficient　R-tree-based　compatible　routing　region　partitioning　algorithm　for　collecting　routable　regions,　which　offers　robust　support　for　ideal　parallel　routing　scheduling.　Then,　taking　into　account　the　effect　of　the　barrel　effect　on　congestion　evaluation　and　the　detrimental　impact　of　loops,　a　congestion-driven　initial　parallel　routing　scheme　is　proposed　to　enhance　routability　in　the　triaxial　pattern　routing　structure.　After　that,　we　develop　an　accurate　congestion　estimation　model　and　an　optimized　path-searching　scheme,　which　are　instrumental　in　effectively　managing　smaller　congestion　gradient　variations　and　guiding　efficient　congestion　reduction.　We　evaluate　the　performance　of　our　algorithm　on　the　ISPD　2018　and　ISPD　2019　contest　benchmark　suites　and　compare　it　with　the　state-of-the-art　work.　Experimental　results　show　that　our　proposed　algorithm　significantly　reduces　71%　overflows,　improving　65%　running　time,　and　the　total　wirelength　is　even　smaller.