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The decomposition of multiplexers (MUXes) implies the representation of n-to-1 MUXes in terms of basic logic gates. This decomposition significantly impacts the performance of the subsequent optimization and matching in technology mapping. In this brief, we propose a network-architecture-aware multiplexer decomposition that decomposes an n-to-1 MUX into one of two significantly distinct architectures. Specially, a delay-evaluation-based guidance scheme estimates the total delay of the two architectures and then selects the optimal architecture for decomposing. Experimental results demonstrate that our algorithm outperforms Yosys and Design Compiler. © 2004-2012 IEEE.
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IEEE Transactions on Circuits and Systems II: Express Briefs
ISSN： 1549-7747
Year： 2024
Issue： 9
Volume： 71
Page： 4201-4205
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JCR@2023
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ESI Highly Cited Papers on the List： 0 Unfold All
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30 Days PV： 3
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