Reference　placement　is　promising　to　handle　the　increasing　complexity　in　printed　circuit　board　(PCB)　designs,　which　aims　to　find　the　isomorphism　of　the　placed　template　in　component　combination　to　reuse　the　placement.　In　this　paper,　we　convert　the　netlist　information　into　a　graph　and　then　model　the　reference　placement　as　a　subgraph　matching　problem.　Since　the　state-of-the-art　subgraph　matching　methods　usually　recursively　search　the　solutions　and　suffer　from　high　time　and　memory　consumption　in　large-scale　designs,　we　develop　a　novel　subgraph　matching　algorithm　D2BS　with　diversity　tolerance　and　improved　backtracking　to　guarantee　matching　quality　and　efficiency.　The　D2BS　algorithm　is　founded　on　a　data　structure　called　the　candidate　space　(CS)　structure.　We　build　and　filter　the　candidate　set　for　each　query　node　according　to　our　designed　features　to　construct　the　CS　structure.　During　the　CS　optimization　process,　a　graph　diversity　tolerance　strategy　is　adopted　to　achieve　efficient　inexact　matching.　Then,　hierarchical　matching　is　developed　to　search　the　template　embeddings　in　the　CS　structure　guided　by　branch　backtracking　and　matched-node　snatching　strategies.　Based　on　the　industrial　PCB　designs,　experimental　results　show　that　D2BS　outperforms　the　state-of-the-art　subgraph　matching　method　in　matching　accuracy　and　running　time.　©　The　Author(s),　under　exclusive　licence　to　Springer　Science+Business　Media,　LLC,　part　of　Springer　Nature　2024.