This　research　proposes　an　innovative　intelligent　detection　methodology　tailored　for　the　high-speed　train　catenary　system,　leveraging　FPGA-accelerated　MobileNetV2.　Exploiting　the　exceptional　computational　capabilities　of　the　MobileNetV2　convolutional　neural　network,　the　methodology　incorporates　Quantization　Aware　Training　(QAT)　to　judiciously　compress　the　comprehensive　network　parameters　to　one-fourth　of　the　original　configuration,　ensuring　judicious　and　efficient　intelligent　detection　for　the　high-speed　train　catenary　system.　Notably,　the　entirety　of　network　weights　is　strategically　allocated　to　the　on-chip　resources　of　the　FPGA,　effectively　circumventing　constraints　inherent　to　off-chip　storage　bandwidth.　This　strategic　allocation　addresses　power　consumption　challenges　linked　to　accessing　off-chip　storage　resources,　culminating　in　a　substantial　augmentation　of　the　real-time　operational　efficiency　of　the　network.The　proposed　system,　an　intricately　tuned　and　energy-efficient　Lightweight　Convolutional　Neural　Network　(MobileNetV2)　recognition　system,　is　meticulously　implemented　on　the　Xilinx　Virtex-7　VC707　development　board.　Operating　seamlessly　at　a　clock　frequency　of　200Hz,　the　system　attains　an　impressive　throughput　of　170.06　GOP/s　with　a　mere　power　consumption　of　6.13W.　The　resultant　energy　efficiency　ratio　excels　at　27.74　GOP/s/W,　significantly　outpacing　the　CPU　by　a　factor　of　92　and　the　GPU　by　a　factor　of　25.　These　findings　underscore　substantial　performance　advantages　when　juxtaposed　with　alternative　implementations.　　©　2024　ACM.