Translated Title
Research and Design of High-performance MobileNet Hardware Accelerator Based on FPGA
Translated Abstract
Most of the existing neural networks have complex models.They are difficult to be applied to practical sce-narios such as mobile terminals due to the large amount of model parameters and calculations.Therefore,this paper chooses the lightweight neural network MobileNet to use the high-performance and reconfigurable FPGA platform for hardware acceleration design.The accelerator is optimized through parallel deployment,pipeline design,quantization strategy and other methods.In view of the large amount of DSP resource consumption caused by improving the paral-lelism,this paper optimizes the multiplication process of calculation through DSP optimized coding,thus reducing the DSP resource consumption by 44.8％.The experimental results show that the reasoning speed of 129.6 FPS is realized on Xilinx ZCU102,and the overall performance reaches 147.4 GOP/S.
Translated Keyword
FPGA
hardware acceleration
MobileNet
neural networks
Access Number
WF:perioarticalzgjcdl202403007
