Field-programmable　gate　array　(FPGA)　is　an　ideal　candidate　for　accelerating　graph　neural　networks　(GNNs).　However,　FPGA　reconfiguration　is　a　time-consuming　process　when　updating　or　switching　between　diverse　GNN　models　across　different　applications.　This　paper　proposes　a　highly　integrated　FPGA-based　overlay　processor　for　GNN　accelerations.　Graph-OPU　provides　excellent　flexibility　and　software-like　programmability　for　GNN　end-users,　as　the　executable　code　of　GNN　models　are　automatically　compiled　and　reloaded　without　requiring　FPGA　reconfiguration.　First,　we　customize　the　instruction　sets　for　the　inference　qprocess　of　different　GNN　models.　Second,　we　propose　a　microarchitecture　ensuring　a　fully-pipelined　process　for　GNN　inference.　Third,　we　design　a　unified　matrix　multiplication　to　process　sparse-dense　matrix　multiplication　and　general　matrix　multiplication　to　increase　the　Graph-OPU　performance.　Finally,　we　implement　a　hardware　prototype　on　the　Xilinx　Alveo　U50　and　test　the　mainstream　GNN　models　using　various　datasets.　Graph-OPU　takes　an　average　of　only　2　minutes　to　switch　between　different　GNN　models,　exhibiting　average　128×　speedup　compared　to　related　works.　In　addition,　Graph-OPU　outperforms　state-of-the-art　end-to-end　overlay　accelerators　for　GNN,　reducing　latency　by　an　average　of　1.36×　and　improving　energy　efficiency　by　an　average　of　1.41×.　Moreover,　Graph-OPU　achieves　up　to　1654×　and　63×　speedup,　as　well　as　up　to　5305×　and　422×　energy　efficiency　boosts,　compared　to　implementations　on　CPU　and　GPU,　respectively.　To　the　best　of　our　knowledge,　Graph-OPU　represents　the　first　in-depth　study　of　an　FPGA-based　overlay　processor　for　GNNs,　offering　high　flexibility,　speedup,　and　energy　efficiency.　©　2023　IEEE.