A lock time improved type-I PLL using a wide-bandwidth PLL-like time domain digital-to-analog convertor - Details

author：

Li, Fanyang (Li, Fanyang.) ^[1] (Scholars：李凡阳) | Zhang, Yanqing (Zhang, Yanqing.) ^[2] | Huang, Gaowen (Huang, Gaowen.) ^[3]

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Abstract：

In　this　paper,　a　type-I　phase-locked　loop　(PLL)　is　proposed.　Compared　with　the　conventional　PLL　based　on　an　active-RC　filter,　the　lock　time　is　able　to　be　optimized　by　means　of　replacing　it　with　a　wide-bandwidth　PLL-like　time-to-analog　convertor　(TAC)　in　the　proposed　PLL.　To　demonstrate　the　efficiency　of　the　structure,　the　proposed　PLL　is　simulated　with　SMIC　180nm　standard　CMOS　process,　achieving　the　lock　time　is　less　than　3μs　and　the　reference　spur　is　less　than　-51dB,　which　consumes　3.8　mW　under　1.2　V　power　supply　and　the　core　layout　area　of　the　PLL　is　about　0.13mm2.　©　2022　IEEE.

Keyword：

Bandwidth Digital to analog conversion Locks (fasteners) Phase locked loops

Community：

[ 1 ] [Li, Fanyang]Fuzhou University, School of Physics and Information Engineering, 350108, China
[ 2 ] [Zhang, Yanqing]Fuzhou University, School of Physics and Information Engineering, 350108, China
[ 3 ] [Huang, Gaowen]Fuzhou University, School of Physics and Information Engineering, 350108, China