As　the　scale　of　integrated　circuits　grows,　the　number　of　nets　greatly　increases,　which　makes　the　runtime　of　layer　assignment　algorithm　increase　and　becomes　an　important　limiting　factor　of　efficient　routing　algorithm.　Besides,　in　the　manufacture,　vias　always　take　high　cost.　Accordingly,　this　paper　presents　two　strategies　to　reduce　runtime　and　the　number　of　vias:　(1)　an　efficient　region-division　based　parallel　strategy,　which　realizes　load　balancing　of　parallel　routing　to　improve　the　efficiency　of　routing　algorithm;　(2)　an　equivalent　routing　solution　aware　via　optimization　strategy,　which　determines　the　priority　of　each　net　in　using　routing　resource　to　reduce　the　number　of　vias　of　layer　assignment.　Furthermore,　combining　the　above　two　strategies,　this　paper　proposes　a　via-aware　parallel　layer　assignment　algorithm　for　very　large　scale　integration　(VLSI)　physical　design.　The　experimental　results　show　that　the　proposed　algorithm　is　able　to　optimize　the　number　of　vias　significantly　and　reduce　runtime　simultaneously.　©　2022　Chinese　Institute　of　Electronics.　All　rights　reserved.