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author:

Huang, Xing (Huang, Xing.) [1] | Guo, Wenzhong (Guo, Wenzhong.) [2] (Scholars:郭文忠) | Chen, Zhisheng (Chen, Zhisheng.) [3] | Li, Bing (Li, Bing.) [4] | Ho, Tsung-Yi (Ho, Tsung-Yi.) [5] | Schlichtmann, Ulf (Schlichtmann, Ulf.) [6]

Indexed by:

EI SCIE

Abstract:

System-architecture design optimization of flow-based microfluidic biochips has been extensively investigated over the past decade. Most of the prior work, however, is still based on chip architectures with dedicated storage units and this, not only limits the performance of biochips, but also increases their fabrication cost. To overcome this limitation, a distributed channel-storage architecture can be implemented, where fluid samples can be cached temporarily in flow channels instead of using a dedicated storage. This new concept of fluid storage, however, requires a careful arrangement of fluid samples to enable the channels to fulfill the dual functions of transportation and caching. Moreover, to avoid cross-contamination between different fluidic flows, wash operations are necessary to remove the residue left in flow channels. In this article, we formulate the first practical system level design and wash optimization problem for microfluidic biochips with distributed channel storage architecture, considering high-level synthesis, physical design, and wash optimization simultaneously, and present a top-down design flow to solve this problem systematically. Given the protocol of a biochemical application and the corresponding design requirements, our goal is to generate a chip architecture with low fabrication cost. Meanwhile the biochemical application can be executed efficiently with an optimized wash scheme. Experimental results on multiple benchmarks confirm that our approach leads to short completion time of biochemical applications, low chip cost, as well as high wash efficiency.

Keyword:

Biochips Computer architecture distributed channel-storage architecture Microfluidic biochips Mixers Optimization system-level design System-level design Transportation Valves wash optimization

Community:

  • [ 1 ] [Huang, Xing]Tech Univ Munich, Chair Elect Design Automat, D-80333 Munich, Germany
  • [ 2 ] [Li, Bing]Tech Univ Munich, Chair Elect Design Automat, D-80333 Munich, Germany
  • [ 3 ] [Schlichtmann, Ulf]Tech Univ Munich, Chair Elect Design Automat, D-80333 Munich, Germany
  • [ 4 ] [Guo, Wenzhong]Fuzhou Univ, Coll Math & Comp Sci, Fuzhou 350116, Fujian, Peoples R China
  • [ 5 ] [Chen, Zhisheng]Fuzhou Univ, Coll Math & Comp Sci, Fuzhou 350116, Fujian, Peoples R China
  • [ 6 ] [Ho, Tsung-Yi]Natl Tsing Hua Univ, Dept Comp Sci, Hsinchu 30013, Taiwan

Reprint 's Address:

  • 郭文忠

    [Guo, Wenzhong]Fuzhou Univ, Coll Math & Comp Sci, Fuzhou 350116, Fujian, Peoples R China

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Source :

IEEE TRANSACTIONS ON COMPUTERS

ISSN: 0018-9340

Year: 2022

Issue: 2

Volume: 71

Page: 464-478

3 . 7

JCR@2022

3 . 6 0 0

JCR@2023

ESI Discipline: COMPUTER SCIENCE;

ESI HC Threshold:61

JCR Journal Grade:2

CAS Journal Grade:2

Cited Count:

WoS CC Cited Count: 13

SCOPUS Cited Count: 22

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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