As　the　scale　of　VLSI　circuits　increases　rapidly,　multi-FPGA　prototyping　systems　have　been　widely　used　for　logic　verification.　Due　to　the　limited　number　of　connections　between　FPGAs,　however,　the　routability　of　prototyping　systems　is　a　bottleneck.　As　a　consequence,　timing　division　multiplexing　(TDM)　technique　has　been　proposed　to　improve　the　usability　of　prototyping　systems,　but　it　causes　a　dramatic　increase　in　system　delay.　In　this　paper,　we　propose　ALIFRouter,　a　practical　architecture-level　inter-FPGA　router,　to　improve　the　chip　performance　by　reducing　the　corresponding　system　delay.　ALIFRouter　consists　of　three　major　stages,　including　i)　routing　topology　generation,　ii)　TDM　ratio　assignment,　and　iii)　system　delay　optimization.　Additionally,　a　multi-thread　parallelization　method　is　integrated　into　the　three　stages　to　improve　the　efficiency　of　ALIFRouter.　With　the　proposed　algorithm,　major　performance　indicators　of　multi-FPGA　systems　such　as　signal　multiplexing　ratio　can　be　improved　significantly.　©　2021　EDAA.