Mitigation of cell-to-cell interference in multi-level-cell (MLC) NAND flash memory using correction factors - Details

author：

Shi, Zhifang (Shi, Zhifang.) ^[1] | Fang, Yi (Fang, Yi.) ^[2] | Bu, Yingcheng (Bu, Yingcheng.) ^[3] | Chen, Pingping (Chen, Pingping.) ^[4] (Scholars：陈平平) Unfold

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Abstract：

With　the　size　of　NAND　flash-memory　chips　scaling　down,　cell-to-cell　interference　(CCI),　stemming　from　the　effect　of　parasitic　coupling　capacitance,　has　become　the　primary　source　of　errors　in　reducing　the　reliability　of　flash　memory.　In　this　work,　we　present　two　CCI-mitigating　algorithms　to　eliminate　the　CCI-induced　errors　for　multi-level-cell　(MLC)　flash　memory.　Specifically,　we　attempt　to　introduce　the　so-called　CCI-correcting　factors　to　adjust　the　inaccurately　estimated　CCI　strength　of　conventional　postcompensation　detection　schemes　while　avoiding　high　computational　complexity.　To　acquire　these　CCI-correcting　factors,　two　CCI-mitigating　algorithms,　called　vertical-and-diagonal-direction　correction　(VDDC)　algorithm　and　all-direction　correction　(ADC)　algorithm,　are　presented.　Analytical　and　simulation　results　demonstrate　that　the　proposed　VDDC　and　ADC　schemes　can　effectively　eliminate　the　CCI-induced　errors　with　low　computational　complexity　compared　to　the　state-of-the-art　detection　algorithms.　©　2021　IEEE.

Keyword：

Computational complexity Errors Flash memory Memory architecture NAND circuits

Community：

[ 1 ] [Shi, Zhifang]Guangdong University of Technology, Guangzhou, China
[ 2 ] [Fang, Yi]Guangdong University of Technology, Guangzhou, China
[ 3 ] [Bu, Yingcheng]Guangdong University of Technology, Guangzhou, China
[ 4 ] [Chen, Pingping]Fuzhou University, Department of Electronic Information, Fuzhou, China