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author:

Chen, Jianli (Chen, Jianli.) [1] | Chang, Yao-Wen (Chang, Yao-Wen.) [2] | Wu, Yen-Yi (Wu, Yen-Yi.) [3]

Indexed by:

SCIE

Abstract:

Mixed-cell-height circuits have prevailed in advanced technology to address various design requirements. Along with device scaling, complex minimum-implant-area (MIA) constraints arise as an emerging challenge in modern circuit designs, adding to the difficulties in mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells is insufficient for mixed-cell-height designs: 1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength overheads and 2) mixed-height-cell perturbation could cause severe inter-row MIA violations. This article addresses the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intrarow violations by clustering violating mixed-height cells of the same threshold voltage, and then perturb each cluster to obtain a desired cell permutation by applying an efficient, optimal dynamic-programming-based algorithm for a special case and Algorithm DLX for general ones, where a provably constant performance ratio for a mixed-cell-height reshaping problem can be achieved. With a network-flow-based formulation, remaining violating cells are placed in appropriate filler-insertion positions to fix cell violations and minimize area. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Experimental results show that our algorithm can efficiently solve all MIA violations without any extra area overhead.

Keyword:

Detailed placement DLX Implants minimum-implant-area (MIA) mixed-cell-height MOS devices network flow physical design Pins Rails Standards Threshold voltage Timing

Community:

  • [ 1 ] [Chen, Jianli]Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
  • [ 2 ] [Chen, Jianli]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350000, Peoples R China
  • [ 3 ] [Chang, Yao-Wen]Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 106, Taiwan
  • [ 4 ] [Chang, Yao-Wen]Natl Taiwan Univ, Dept Comp Sci & Informat Engn, Taipei 106, Taiwan
  • [ 5 ] [Wu, Yen-Yi]Univ Calif San Diego, San Diego, CA 92093 USA

Reprint 's Address:

  • [Chang, Yao-Wen]Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 106, Taiwan

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Source :

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

ISSN: 0278-0070

Year: 2021

Issue: 10

Volume: 40

Page: 2128-2141

2 . 5 6 5

JCR@2021

2 . 7 0 0

JCR@2023

ESI Discipline: ENGINEERING;

ESI HC Threshold:105

JCR Journal Grade:3

CAS Journal Grade:3

Cited Count:

WoS CC Cited Count: 11

SCOPUS Cited Count: 11

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 2

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