Architecture and software implementation of HDTV video decoder on a singlechip, MPEG decoder - Details

author：

Ye, Y. (Ye, Y..) ^[1] | Li, Y. (Li, Y..) ^[2] | Su, K. (Su, K..) ^[3]

Indexed by：

Scopus

Abstract：

This　paper　presents　the　architecture　and　software　design　of　HDTV　video　decoder　on　a　200-MHz　single-chip　microprocessor.　First,　the　paper　analyzes　the　hardware　architecture　of　video　decoder　system　on　this　MPEG　decoder　and　describes　the　function　of　each　module　in　this　system,　including　the　PES　Parser,　Decode　pipeline,　SC　Analyzer,　and　Display　Processor.　Then　it　gives　the　software　control　and　implementation　of　this　video　decoder.　This　video　decoder　meets　the　requirements　for　MPEG-2　MP@HL　real-time　decoding.　The　outcome　of　this　paper　should　be　helpful　to　the　design　of　HDTV　Set　Top　Box.　©　2006　IEEE.

Keyword：

HDTV; MPEG-2; Set top box; Video decoder

Community：

[ 1 ] [Ye, Y.]Dept. of Information and Communication Engineering, Fuzhou University, Fuzhou, China
[ 2 ] [Li, Y.]Dept. of Information and Communication Engineering, Fuzhou University, Fuzhou, China
[ 3 ] [Su, K.]Dept. of Information and Communication Engineering, Fuzhou University, Fuzhou, China

Reprint 's Address：

[Ye, Y.]Dept. of Information and Communication Engineering, Fuzhou University, Fuzhou, China

Email：

yeyuhuang@fzu.edu.cn

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Source ：

Proceedings - Computer Graphics, Imaging and Visualisation: Techniques and Applications, CGIV'06

Year： 2006

Volume： 2006

Page： 226-230

Language： English

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SCOPUS Cited Count： 5

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