Design of a novel all-CMOS low power voltage reference circuit - Details

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Xu, Y. (Xu, Y..) ^[1] | Hu, W. (Hu, W..) ^[2] | Huang, F. (Huang, F..) ^[3] | Huang, J. (Huang, J..) ^[4]

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Abstract：

A　new　low-power　voltage　reference　circuit　was　proposed　using　the　SMIC　0.18um　standard　CMOS　process　technology.　The　resulting　voltage　is　equal　to　the　extrapolated　threshold　voltage　of　a　MOSFET　at　0K,　which　was　about　620mV　for　this　process.　Cadence　Spectre　simulation　results　show　that　the　temperature　coefficient　of　the　output　voltage　was　12.9ppm/°　in　a　range　from　-20　to　80　°.　The　line　sensitivity　was　328ppm/V　in　a　supply　voltage　range　of　1.2-3V.　Meanwhile　-　68　dB　@　100Hz　of　the　power　supply　rejection　ratio　(PSRR)　is　reached　and　it　merely　consumes　0.21　μ　W　of　power.　The　proposed　circuit　is　full　composed　of　CMOS　devices　without　any　use　of　resistors,　which　enjoys　the　merits　of　low　power　consumption　and　small　chip　area.　©　2013　IEEE.

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[ 1 ] [Xu, Y.]Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350002, China
[ 2 ] [Xu, Y.]Fujian Integrated Circuit Design Center, Fuzhou, China
[ 3 ] [Hu, W.]Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350002, China
[ 4 ] [Hu, W.]Fujian Integrated Circuit Design Center, Fuzhou, China
[ 5 ] [Huang, F.]Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350002, China
[ 6 ] [Huang, F.]Fujian Integrated Circuit Design Center, Fuzhou, China
[ 7 ] [Huang, J.]Department of Physics and Information Engineering, Fuzhou University, Fuzhou 350002, China
[ 8 ] [Huang, J.]Fujian Integrated Circuit Design Center, Fuzhou, China

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Proceedings of International Conference on ASIC

ISSN： 2162-7541

Year： 2013

Language： English

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