In　this　paper,　an　on-chip　clock　(OCC)　controller　with　bypass　function　based　on　an　internal　phase-locked　loop　(PLL)　is　designed　to　test　the　faults　in　system　on　chip　(SOC),　such　as　the　transition-delay　faults　and　the　stuck-at　faults.　A　clock　chain　logic　which　can　eliminate　the　metastable　state　is　realized　to　generate　an　enable　signal　for　the　OCC　controller,　and　then,　the　test　pattern　is　generated　by　the　automatic　test　pattern　generation　(ATPG)　tools.　Next,　the　scan　test　pattern　is　simulated　by　the　Synopsys　tool　and　the　correctness　of　the　design　is　verified.　The　result　shows　that　the　design　of　at-speed　scan　test　in　this　paper　is　high　efficient　for　detecting　the　timingrelated　defects.　Finally,　the　89.29　percent　transition-delay　fault　coverage　and　the　94.50　percent　stuck-at　fault　coverage　are　achieved,　and　it　is　successfully　applied　to　an　integrated　circuit　design.　©　2013　Trans　Tech　Publications　Ltd,　Switzerland.