It　is　very　important　to　detect　transition-delay　faults　and　stuck-at　faults　in　system　on　chip　(SoC)　under　90　nm　processing　technology,　and　the　transition-delay　faults　can　only　be　detected　by　using　an　at-speed　testing　method.　In　this　paper,　an　on-chip　clock　(OCC)　controller　with　a　bypass　function　based　on　an　internal　phase-locked　loop　is　designed　to　test　faults　in　SoC.　Furthermore,　a　clock　chain　logic　which　can　eliminate　the　metastable　state　is　realized　to　generate　an　enable　signal　for　the　OCC　controller,　and　then,　the　test　pattern　is　generated　by　automatic　test　pattern　generation　(ATPG)　tools.　Next,　the　scan　test　pattern　is　simulated　by　using　the　Synopsys　tool　and　the　correctness　of　the　design　is　verified.　The　result　shows　that　the　design　of　an　at-speed　scan　test　in　this　paper　is　highly　efficient　for　detecting　timing-related　defects.　Finally,　the　89.29%　transition-delay　fault　coverage　and　the　94.50%　stuck-at　fault　coverage　are　achieved,　and　it　is　successfully　applied　to　an　integrated　circuit　design.　©　2013　Chinese　Institute　of　Electronics.