Floorplanning　is　the　first　stage　of　the　very　large　scale　integrated-circuit　(VLSI)　physical　design　process,　the　resultant　quality　of　this　stage　is　very　important　for　successive　design　stages.　From　the　computational　point　of　view,　VLSI　floorplanning　is　an　NP-hard　problem.　In　this　paper,　a　hybrid　genetic　algorithm　(HGA)　for　a　non-slicing　and　hard-module　VLSI　floorplanning　problem　is　presented.　This　HGA　uses　an　effective　genetic　search　method　to　explore　the　search　space　and　an　efficient　local　search　method　to　exploit　information　in　the　search　region.　Experimental　results　on　MCNC　benchmarks　[16]　show　that　the　HGA　is　effective　and　promising　in　building　block　layout　application.　©2010　IEEE.