The　floorplanning　is　a　critical　phase　in　very　large-scale　integrated-circuit(VLSI)　phsical　design.　It　determines　the　topology　of　layout,　and　it　aims　to　arrange　a　set　of　rectangular　modules　on　a　chip　so　as　to　optimize　the　chip　area,　wirelength,　etc.　This　problem　is　known　to　be　NP-hard,　and　has　received　much　attention　in　recent　years.　B*-tree　representation　is　adopted　in　this　paper.　Based　on　the　concept　of　evolutionary　algorithm　and　simulated　annealing,　a　hybrid　evolutionary　algorithm(ESA)　is　proposed.　It　is　effective　to　explore　solution　space　and　locate　the　optimal　solution.　The　effectiveness　of　our　method　is　demonstrated　on　several　cases　of　MCNC　benchmarks.　©2010　IEEE.