As　the　scale　of　VLSI　circuits　and　fabrication　costs　increase　rapidly,　multi-FPGA　prototyping　systems　are　widely　adopted　in　industry　to　make　logic　verification　faster　and　cheaper.　Since　routing　signals　can　usually　exceed　the　number　of　I/O　pins　in　an　FPGA,　timing　division　multiplexing　(TDM)　technique　is　required　to　solve　this　problem.　FPGA　routing　for　developing　a　prototyping　system　is　a　big　challenge　due　to　the　signal　delay　of　TDM.　This　paper　presents　MSFRoute,　a　multi-stage　FPGA　routing　framework　for　timing　division　multiplexing　technique,　to　optimize　the　signal　delay　and　the　routability　for　prototyping　systems.　In　this　work,　a　TDM　ratios　assignment　algorithm　with　an　efficient　parallelization　method　is　proposed　to　optimize　inter-FPGA　signal　delay.　Meanwhile,　we　propose　a　practical　system　clock　period　optimization　method　to　solve　critical　signal　delay　problem.　Experimental　results　show　that　our　routing　framework　reduces　TDM　ratios　by　up　to　88.3%　with　an　average　reduction　rate　of　41.8%.　With　the　proposed　parallelization　method,　total　flow　of　MSFRoute　can　get　up　to　4.38X　speedup　with　a　2.77X　speedup　on　average.　©　2020　Association　for　Computing　Machinery.