Previous　SRAM-based　computing-in-memory　(SRAM-CIM)　macros　suffer　small　read　margins　for　high-precision　operations,　large　cell　array　area　overhead,　and　limited　compatibility　with　many　input　and　weight　configurations.　This　work　presents　a　1-to-8-bit　configurable　SRAM　CIM　unit-macro　using:　1)　a　hybrid　structure　combining　6T-SRAM　based　in-memory　binary　product-sum　(PS)　operations　with　digital　near-memory-computing　multibit　PS　accumulation　to　increase　read　accuracy　and　reduce　area　overhead;　2)　column-based　place-value-grouped　weight　mapping　and　a　serial-bit　input　(SBIN)　mapping　scheme　to　facilitate　reconfiguration　and　increase　array　efficiency　under　various　input　and　weight　configurations;　3)　a　self-reference　multilevel　reader　(SRMLR)　to　reduce　read-out　energy　and　achieve　a　sensing　margin　2　$\times　$　that　of　the　mid-point　reference　scheme;　and　4)　an　input-aware　bitline　voltage　compensation　scheme　to　ensure　successful　read　operations　across　various　input-weight　patterns.　A　4-Kb　configurable　6T-SRAM　CIM　unit-macro　was　fabricated　using　a　55-nm　CMOS　process　with　foundry　6T-SRAM　cells.　The　resulting　macro　achieved　access　times　of　3.5　ns　per　cycle　(pipeline)　and　energy　efficiency　of　0.6-40.2　TOPS/W　under　binary　to　8-b　input/8-b　weight　precision.　©　1966-2012　IEEE.