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author:

Zhang, Z. (Zhang, Z..) [1] | Chen, J.-J. (Chen, J.-J..) [2] | Si, X. (Si, X..) [3] | Tu, Y.-N. (Tu, Y.-N..) [4] | Su, J.-W. (Su, J.-W..) [5] | Huang, W.-H. (Huang, W.-H..) [6] | Wang, J.-H. (Wang, J.-H..) [7] | Wei, W.-C. (Wei, W.-C..) [8] | Chiu, Y.-C. (Chiu, Y.-C..) [9] | Hong, J.-M. (Hong, J.-M..) [10] | Sheu, S.-S. (Sheu, S.-S..) [11] | Li, S.-H. (Li, S.-H..) [12] | Liu, R.-S. (Liu, R.-S..) [13] | Hsieh, C.-C. (Hsieh, C.-C..) [14] | Tang, K.-T. (Tang, K.-T..) [15] | Chang, M.-F. (Chang, M.-F..) [16]

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Scopus

Abstract:

This work presents a 1-to-8 bit configurable SRAM CIM unit-macro using (1) a hybrid structure combining 6T-SRAM in-memory binary product-sum (IMBPS) with digital near-memory-computing multi-bit-PS accumulation (DNMPSA) to achieve high read accuracy and compact area, (2) a column-based place-value-grouped weight mapping (CPVGWM) and serial-bit input mapping (SBIN) scheme to facilitate reconfiguration and increase array efficiency for various input/weight precision. A 4Kb configurable 6T-SRAM CIM unit-macro was fabricated using a 55nm CMOS process and foundry 6T cells. The resulting macro achieved 3.5ns access time with 3b PS outputs and gained a 3.91-50x improvement in figure-of-merit, compared to previous SRAM-CIMs. © 2019 IEEE.

Keyword:

AI edge processor; CIM; CNN; SRAM

Community:

  • [ 1 ] [Zhang, Z.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 2 ] [Zhang, Z.]Fuzhou University, Fuzhou, China
  • [ 3 ] [Chen, J.-J.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 4 ] [Si, X.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 5 ] [Tu, Y.-N.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 6 ] [Su, J.-W.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 7 ] [Su, J.-W.]Industrial Technology Research Institute, Hsinchu, Taiwan
  • [ 8 ] [Huang, W.-H.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 9 ] [Wang, J.-H.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 10 ] [Wei, W.-C.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 11 ] [Chiu, Y.-C.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 12 ] [Hong, J.-M.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 13 ] [Sheu, S.-S.]Industrial Technology Research Institute, Hsinchu, Taiwan
  • [ 14 ] [Li, S.-H.]Industrial Technology Research Institute, Hsinchu, Taiwan
  • [ 15 ] [Liu, R.-S.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 16 ] [Hsieh, C.-C.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 17 ] [Tang, K.-T.]National Tsing Hua University, Hsinchu, Taiwan
  • [ 18 ] [Chang, M.-F.]National Tsing Hua University, Hsinchu, Taiwan

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Source :

Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019

Year: 2019

Page: 217-218

Language: English

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

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Chinese Cited Count:

30 Days PV: 3

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