A novel design of PIE decoding with multiple CRC circuit for RFID tag - Details

author：

Huang, Feng Ying (Huang, Feng Ying.) ^[1] | Wang, Jun (Wang, Jun.) ^[2] | Xu, Yu Sen (Xu, Yu Sen.) ^[3] | Huang, Ji Wei (Huang, Ji Wei.) ^[4] (Scholars：黄继伟)

Indexed by：

EI Scopus

Abstract：

This　paper　proposes　a　new　synchronized　serial-parallel　CRC(Cycle　Redundancy　Check)　with　PIE(Pulse　Interval　Encoding)　decoding　circuit　for　the　UHF(Ultra-High　Frequency)　RFID(Radio　Frequency　Identification),　which　is　based　on　the　ISO/IEC　18000-6C　standards　protocol.　The　parallel　algorithm　of　CRC　circuit　is　derived,　and　the　serial　or　parallel　CRC　circuit　on　RFID　tag　chip　is　evaluated　in　this　paper.　Finally,　the　designed　circuit　is　simulated　and　analyzed　on　the　FPGA　platform.　Simulation　results　show　that　the　proposed　circuit　meets　the　communication　requirement　of　the　protocol　and　addresses　the　problem　of　low　data　processing　rate　of　conventional　serial　CRC　circuit,　as　well　as　implements　1　to　8　degree　of　parallelism　of　the　parallel　CRC　circuit　for　UHF　RFID.　©　(2013)　Trans　Tech　Publications,　Switzerland.

Keyword：

Data processing Decoding Electric network analysis Field programmable gate arrays (FPGA) Manufacture Network protocols Radio frequency identification (RFID)

Community：

[ 1 ] [Huang, Feng Ying]Depatment of Physics and Information Engineering, Fuzhou University, China
[ 2 ] [Huang, Feng Ying]Fujian Integrated Circuit Design Center, Fuzhou 350002, China
[ 3 ] [Wang, Jun]Fujian Integrated Circuit Design Center, Fuzhou 350002, China
[ 4 ] [Xu, Yu Sen]Depatment of Physics and Information Engineering, Fuzhou University, China
[ 5 ] [Xu, Yu Sen]Fujian Integrated Circuit Design Center, Fuzhou 350002, China
[ 6 ] [Huang, Ji Wei]Depatment of Physics and Information Engineering, Fuzhou University, China
[ 7 ] [Huang, Ji Wei]Fujian Integrated Circuit Design Center, Fuzhou 350002, China