With　the　increasing　design　requirements　of　modern　circuits,　a　standard-cell　library　often　contains　cells　of　different　row　heights　to　address　various　trade-offs　among　performance,　power,　and　area.　However,　maintaining　all　standard　cells　with　integer　multiples　of　a　single-row　height　could　cause　some　area　overheads　and　increase　power　consumption.　In　this　paper,　we　present　an　analytical　placer　to　directly　consider　a　circuit　design　with　non-integer　multiple-height　standard　cells　and　additional　layout　constraints.　The　region　of　different　cell　heights　is　adaptively　generated　by　the　global　placement　result.　In　particular,　an　exact　penalty　iterative　shrinkage　and　thresholding　(EPIST)　algorithm　is　employed　to　efficiently　optimize　the　global　placement　problem.　The　convergence　of　the　algorithm　is　proved,　and　the　acceleration　strategy　is　proposed　to　improve　the　performance　of　our　algorithm.　Compared　with　the　state-of-the-art　works,　experimental　results　based　on　the　2017　CAD　Contest　at　ICCAD　benchmarks　show　that　our　algorithm　achieves　the　best　wirelength　and　area　for　every　benchmark.　In　particular,　our　proposed　EPIST　algorithm　provides　a　new　direction　for　effectively　solving　large-scale　nonlinear　optimization　problems　with　non-smooth　terms,　which　are　often　seen　in　real-world　applications.　©　2020　IEEE.