Introduction:　In　Very　Large　Scale　Integration　(VLSI),　routing　is　the　process　of　making　connections　among　objects　reasonable　in　the　specific　area　and　some　cost　metrics　(i.e.,　routability)　are　optimized.　It　is　a　crucial　step　in　VLSI　physical　design　as　the　performance　of　a　chip　depends　on　the　routing　results　heavily.　Methods:　In　this　paper,　by　congestion-based　routing　modeling,　a　multilevel　based　routing　optimization　method　is　developed　to　solve　the　VLSI　routing　problem.　In　the　routing　optimization　method,　the　global　and　the　detailed　routing　phases　run　alternately.　At　each　level　of　the　multilevel　framework,　global　and　detailed　routing　paths　for　each　local　net　are　identified.　Moreover,　some　strategies　are　used　to　improve　the　routing　results.　Results:　After　detailed　routing,　a　resource　estimation　is　designed　to　obtain　more　accurate　routing　resources　for　the　next　level,　and　an　ultimate　congestion　strategy　is　used　to　improve　the　pass　rate　of　the　nets.　Experimental　results　on　standard　tested　benchmarks　demonstrate　that　the　proposed　method　is　effective　and　efficient　to　improve　the　routability　of　a　chip.　©　2018　Bentham　Science　Publishers.