We　describe　a　new　RDF-2019　release　of　the　IEEE　CEDA　DATC　Robust　Design　Flow　(RDF).　RDF-2019　enhances　the　DATC　RDF　to　span　the　entire　RTL-to-GDS　IC　implementation　flow,　from　logic　synthesis　to　detailed　routing.　The　new　release　represents　a　significant　revision　of　the　previously-reported　RDF-2018　flow.　Noteworthy　vertical　extensions　include　addition　of　logic　synthesis　starting　from　pure　behavioral　RTL　Verilog　RTL;　floorplanning　that　includes　initial　DEF　creation,　I/O　placement　and　PDN　layout　generation;　and　clock　tree　synthesis　between　placement　legalization　and　global　routing.　A　number　of　horizontal　extensions　to　RDF　are　achieved　by　incorporating　additional　tool　options　at　the　static　timing　analysis,　global　placement,　gate　sizing,　and　detailed　routing　stages　of　the　flow.　Further,　for　the　first　time,　multiple　open-source　realizations　of　the　entire　RDF　tool　chain　are　available.　Last,　RDF-2019　provides　significantly　enhanced　support　of　and　interoperability　with　industry-standard　tools　and　design　formats　(LEF/DEF,　SPEF,　Liberty,　SDC,　etc.).　We　illustrate　the　configuration　and　use　of　RDF-2019,　with　example　results　on　open　as　well　as　commercial　design　enablements.