This　work　presents　a　1-to-8　bit　configurable　SRAM　CIM　unit-macro　using　(1)　a　hybrid　structure　combining　6T-SRAM　in-memory　binary　product-sum　(IMBPS)　with　digital　near-memory-computing　multi-bit-PS　accumulation　(DNMPSA)　to　achieve　high　read　accuracy　and　compact　area,　(2)　a　column-based　place-value-grouped　weight　mapping　(CPVGWM)　and　serial-bit　input　mapping　(SBIN)　scheme　to　facilitate　reconfiguration　and　increase　array　efficiency　for　various　input/weight　precision.　A　4Kb　configurable　6T-SRAM　CIM　unit-macro　was　fabricated　using　a　55nm　CMOS　process　and　foundry　6T　cells.　The　resulting　macro　achieved　3.5ns　access　time　with　3b　PS　outputs　and　gained　a　3.91-50x　improvement　in　figure-of-merit,　compared　to　previous　SRAM-CIMs.