By　ignoring　some　cell　overlaps,　global　placement　computes　the　best　position　for　each　cell　to　minimize　the　wirelength.　It　is　an　important　stage　in　very　large　scale　integration　(VLSI)　physical　design,　since　circuit　performance　heavily　depends　on　the　placement　results.　In　this　paper,　we　propose　an　augmented　Lagrangian　method　to　solve　the　VLSI　global　placement　problem.　In　the　proposed　method,　a　cautious　dynamic　density　weight　strategy　is　used　to　balance　the　wirelength　objective　and　the　density　constraints,　and　an　adaptive　step　size　is　used　to　obtain　a　trade-off　between　runtime　and　solution　quality.　The　proposed　method　is　tested　on　the　IBM　mixed-size　benchmarks　and　the　International　Symposium　on　Physical　Design　2006　placement　contest　benchmarks.　Experimental　results　show　that　our　global　placement　method　outperforms　the　state-of-the-art　placement　approaches　in　terms　of　solution　quality　on　most　of　the　benchmarks.