Routing　is　a　complex　and　critical　stage　in　the　physical　design　of　Very　Large　Scale　Integration　(VLSI),　minimizing　interconnect　length　and　delay　to　optimize　overall　chip　performance.　With　the　rapid　development　of　modern　technology,　VLSI　routing　faces　enormous　challenges　such　as　large　delay,　high　congestion,　and　high-power　consumption.　As　a　rising　optimization　method,　Swarm　Intelligence　(SI)　inspired　from　collective　intelligence　behaviors　through　cooperation　or　interaction　with　the　environment　provides　effectiveness　and　robustness　for　solving　NP-hard　problems.　Many　researchers　have　consequently　used　SI　techniques　to　solve　routing-related　problems　in　VLSI.　This　paper　reviews　the　application　of　several　SI　techniques　to　the　VLSI　routing　filed.　Firstly,　five　commonly　used　SI　techniques　and　related　models,　and　three　classic　routing　problems　are　described:　Steiner　tree　construction,　global　routing　and　detailed　routing.　Then　an　overview　of　the　current　state　of　this　field　is　given　according　to　the　above　categories,　and　the　survey　offers　informative　discussions　from　five　aspects:　1)　Steiner　minimum　tree　construction;　2)　wirelength-driven　routing;　3)　obstacle-avoiding　routing;　4)　timing-driven　routing;　5)　power-driven　routing.　Finally,　under　three　new　technology　models:　X-architecture,　multiple　dynamic　supply　voltage　and　via-pillar,　the　future　development　trends　are　pointed　as　follows:　1)　suggesting　suitable　SI　techniques　to　specific　routing　problems　for　advanced　technology　models;　2)　exploring　new　and　available　SI　techniques　that　have　not　yet　been　applied　to　VLSI　routing.